Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4d2cdcae authored by Jeevan Shriram's avatar Jeevan Shriram Committed by Gerrit - the friendly Code Review server
Browse files

msm: mdss: update mdp clock rate with pingpong split enabled 



When pingpong split is enabled, single DSPP output is driving two
interfaces and MDP clock has to be 2x times the pixel clock. In the
current implementation, pingpong split is not considered in the MDP
clock calculations. This change accounts for pingpong split and update
MDP clock accordingly.

Change-Id: I85a86fa747c908f76bd01faf36fe310d502e2121
Signed-off-by: default avatarJeevan Shriram <jshriram@codeaurora.org>
parent 5dc82e31

drivers/video/msm/mdss/mdss_mdp_ctl.c

+10 −4
Original line number Diff line number Diff line
@@ -730,13 +730,19 @@ static void mdss_mdp_perf_calc_mixer(struct mdss_mdp_mixer *mixer, 
		perf->mdp_clk_rate =

			mdss_mdp_clk_fudge_factor(mixer, perf->mdp_clk_rate);



		if (!pinfo)	/* perf for bus writeback */

		if (!pinfo) {	/* perf for bus writeback */

			perf->bw_overlap =

				fps * mixer->width * mixer->height * 3;

		/* for command mode, run as fast as the link allows us */

		else if ((pinfo->type == MIPI_CMD_PANEL) &&

			 (pinfo->mipi.dsi_pclk_rate > perf->mdp_clk_rate))

			perf->mdp_clk_rate = pinfo->mipi.dsi_pclk_rate;

		} else if (pinfo->type == MIPI_CMD_PANEL) {

			u32 dsi_pclk_rate = pinfo->mipi.dsi_pclk_rate;



			if (is_pingpong_split(mixer->ctl->mfd))

				dsi_pclk_rate *= 2;



			if (dsi_pclk_rate > perf->mdp_clk_rate)

				perf->mdp_clk_rate = dsi_pclk_rate;

		}

	}



	/*