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Commit 404525d5 authored by Maxime Ripard's avatar Maxime Ripard
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clk: sunxi: Add dummy fixed rate clock for Allwinner A1X SoCs 



Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@ti.com>
parent 77b67063
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