Loading arch/arm/boot/dts/qcom/msm8916.dtsi +35 −0 Original line number Diff line number Diff line Loading @@ -1110,6 +1110,41 @@ qcom,bcl { compatible = "qcom,bcl"; }; qcom,mss@4080000 { compatible = "qcom,pil-q6v56-mss"; reg = <0x04080000 0x100>, <0x0194F000 0x3000>, <0x04020000 0x040>, <0x01810000 0x004>; reg-names = "qdsp6_base", "halt_base", "rmb_base", "restart_reg"; interrupts = <0 24 1>; vdd_cx-supply = <&pm8916_s1_corner>; vdd_mx-supply = <&pm8916_l2>; vdd_mx-uV = <1050000>; clocks = <&clock_rpm clk_xo_pil_mss_clk>, <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, <&clock_gcc clk_gcc_boot_rom_ahb_clk>; clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; proxy-clock-names = "xo"; active-clock-names = "iface_clk", "bus_clk", "mem_clk"; qcom,is-loadable; qcom,firmware-name = "modem"; qcom,pil-self-auth; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; /* GPIO output to mss */ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; }; }; &gdsc_venus { Loading Loading
arch/arm/boot/dts/qcom/msm8916.dtsi +35 −0 Original line number Diff line number Diff line Loading @@ -1110,6 +1110,41 @@ qcom,bcl { compatible = "qcom,bcl"; }; qcom,mss@4080000 { compatible = "qcom,pil-q6v56-mss"; reg = <0x04080000 0x100>, <0x0194F000 0x3000>, <0x04020000 0x040>, <0x01810000 0x004>; reg-names = "qdsp6_base", "halt_base", "rmb_base", "restart_reg"; interrupts = <0 24 1>; vdd_cx-supply = <&pm8916_s1_corner>; vdd_mx-supply = <&pm8916_l2>; vdd_mx-uV = <1050000>; clocks = <&clock_rpm clk_xo_pil_mss_clk>, <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, <&clock_gcc clk_gcc_boot_rom_ahb_clk>; clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; proxy-clock-names = "xo"; active-clock-names = "iface_clk", "bus_clk", "mem_clk"; qcom,is-loadable; qcom,firmware-name = "modem"; qcom,pil-self-auth; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; /* GPIO output to mss */ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; }; }; &gdsc_venus { Loading