Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3d09caf9 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "qcom: clock-cpu-8994: Read the CCI voltage plan"

parents 92349a15 f7c5975b

Documentation/devicetree/bindings/arm/msm/clock-cpu-8994.txt

+10 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Required properties: 
			"c1_mux", "cci_mux"

- vdd-a53-supply:	The regulator powering the A53 cluster

- vdd-a57-supply:	The regulator powering the A57 cluster

- vdd-cci-supply:	The regulator powering the CCI cluster

- vdd-pll-supply:	The regulator powering the cluster PLLs

- qcom,a5X-speedbinY-vZ:

			A table of CPU frequency (Hz) to voltage (corner)
@@ -29,6 +30,10 @@ Required properties: 
			the right table is picked from multiple possible tables.

			 'X' is 3 or 7 depending on whether the table is for the

			A53 or A57 cluster.

- qcom,cci-speedbinY-vZ:

			Similar to the qcom,a5X-speedbinY-vZ property described

			above, except this frequency to voltage table is applied

			to the clock for the CCI.

Example:

	clock_cpu: qcom,cpu-clock-8994@f9015000 {

		compatible = "qcom,cpu-clock-8994";
@@ -51,6 +56,11 @@ Example: 
			< 384000000 1>,

			< 787200000 2>,

			<1785600000 3>;

		qcom,cci-speedbin0-v0 =

			<         0 0>,

			< 150000000 1>,

			< 300000000 2>,

			< 600000000 3>;

		clock-names = "xo", "aux_clk";

		clocks = <&clock_rpm clk_cxo_clk_src>,

			 <&clock_gcc clk_gpll0_ao>;

drivers/clk/qcom/clock-cpu-8994.c

+16 −0
Original line number Diff line number Diff line
@@ -674,6 +674,8 @@ static struct mux_clk cci_hf_mux = { 
	},

};



DEFINE_VDD_REGS_INIT(vdd_cci, 1);



static struct div_clk cci_clk = {

	.data = {

		.min_div = 1,
@@ -687,6 +689,7 @@ static struct div_clk cci_clk = { 
	.shift = 5,

	.c = {

		.parent = &cci_hf_mux.c,

		.vdd_class = &vdd_cci,

		.dbg_name = "cci_clk",

		.ops = &clk_ops_div,

		CLK_INIT(cci_clk.c),
@@ -820,6 +823,13 @@ static int cpu_clock_8994_resources_init(struct platform_device *pdev) 
		return PTR_ERR(vdd_a57.regulator[0]);

	}



	vdd_cci.regulator[0] = devm_regulator_get(&pdev->dev, "vdd-cci");

	if (IS_ERR(vdd_cci.regulator[0])) {

		if (PTR_ERR(vdd_cci.regulator[0]) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get the cci vreg\n");

		return PTR_ERR(vdd_cci.regulator[0]);

	}



	c = devm_clk_get(&pdev->dev, "xo_ao");

	if (IS_ERR(c)) {

		if (PTR_ERR(c) != -EPROBE_DEFER)
@@ -906,6 +916,12 @@ static int cpu_clock_8994_driver_probe(struct platform_device *pdev) 
		return ret;

	}



	ret = of_get_fmax_vdd_class(pdev, &cci_clk.c, "qcom,cci-speedbin0-v0");

	if (ret) {

		dev_err(&pdev->dev, "Can't get speed bin for cci\n");

		return ret;

	}



	get_online_cpus();



	ret = of_msm_clock_register(pdev->dev.of_node, cpu_clocks_8994,