Loading arch/arm/boot/dts/qcom/msm8994.dtsi +7 −3 Original line number Diff line number Diff line Loading @@ -1368,6 +1368,7 @@ reg-names = "c0_pll", "c1_pll", "cci_pll", "c0_mux", "c1_mux", "cci_mux"; vdd-a53-supply = <&apc0_vreg_corner>; vdd-a57-supply = <&apc1_vreg_corner>; vdd-cci-supply = <&apc0_vreg_corner>; vdd-dig-supply = <&pm8994_s1_corner_ao>; qcom,a53-speedbin0-v0 = < 0 0>, Loading @@ -1376,9 +1377,12 @@ < 940800000 3>; qcom,a57-speedbin0-v0 = < 0 0>, < 249600000 1>, < 499200000 2>, < 921600000 3>; < 249600000 1>; qcom,cci-speedbin0-v0 = < 0 0>, < 150000000 1>, < 300000000 2>, < 600000000 3>; clock-names = "xo_ao", "aux_clk"; clocks = <&clock_rpm clk_cxo_clk_src_ao>, <&clock_gcc clk_gpll0_ao>; Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +7 −3 Original line number Diff line number Diff line Loading @@ -1368,6 +1368,7 @@ reg-names = "c0_pll", "c1_pll", "cci_pll", "c0_mux", "c1_mux", "cci_mux"; vdd-a53-supply = <&apc0_vreg_corner>; vdd-a57-supply = <&apc1_vreg_corner>; vdd-cci-supply = <&apc0_vreg_corner>; vdd-dig-supply = <&pm8994_s1_corner_ao>; qcom,a53-speedbin0-v0 = < 0 0>, Loading @@ -1376,9 +1377,12 @@ < 940800000 3>; qcom,a57-speedbin0-v0 = < 0 0>, < 249600000 1>, < 499200000 2>, < 921600000 3>; < 249600000 1>; qcom,cci-speedbin0-v0 = < 0 0>, < 150000000 1>, < 300000000 2>, < 600000000 3>; clock-names = "xo_ao", "aux_clk"; clocks = <&clock_rpm clk_cxo_clk_src_ao>, <&clock_gcc clk_gpll0_ao>; Loading