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Commit 382b97be authored by Jack Pham's avatar Jack Pham
Browse files

clk: qcom: Change gcc_usb3_phy_pipe_clk to gate_clk for MSM8992



gcc_usb3_phy_pipe_clk's source could be dynamically gated off at any
time. Thus checking branch_clk status bit could result in stuck on/off
warnings. Since the HW design can handle clock input glitch, model
gcc_usb3_phy_pipe_clk as gate clock instead of branch_clk.

Also add gcc_usb3phy_phy_reset for asserting reset bit previously
associated to gcc_usb3_phy_pipe_clk branch.

This patch is simply a carbon copy of commit c32533e8 (clk: qcom:
Change gcc_usb3_phy_pipe_clk to gate_clk) which was for MSM8994.

Change-Id: I04acef3c936d9591f7517677f8ed382269ad74c7
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 5a2cf19e
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+16 −5
Original line number Diff line number Diff line
@@ -2142,18 +2142,28 @@ static struct branch_clk gcc_usb3_phy_aux_clk = {
	},
};

static struct branch_clk gcc_usb3_phy_pipe_clk = {
	.cbcr_reg = USB3_PHY_PIPE_CBCR,
	.bcr_reg = USB3PHY_PHY_BCR,
	.has_sibling = 1,
static struct gate_clk gcc_usb3_phy_pipe_clk = {
	.en_reg = USB3_PHY_PIPE_CBCR,
	.en_mask = BIT(0),
	.delay_us = 50,
	.base = &virt_base,
	.c = {
		.dbg_name = "gcc_usb3_phy_pipe_clk",
		.ops = &clk_ops_branch,
		.ops = &clk_ops_gate,
		CLK_INIT(gcc_usb3_phy_pipe_clk.c),
	},
};

static struct reset_clk gcc_usb3phy_phy_reset = {
	.reset_reg = USB3PHY_PHY_BCR,
	.base = &virt_base,
	.c = {
		.dbg_name = "gcc_usb3phy_phy_reset",
		.ops = &clk_ops_rst,
		CLK_INIT(gcc_usb3phy_phy_reset.c),
	},
};

static struct branch_clk gcc_usb_hs_ahb_clk = {
	.cbcr_reg = USB_HS_AHB_CBCR,
	.has_sibling = 1,
@@ -2451,6 +2461,7 @@ static struct clk_lookup msm_clocks_gcc_8992[] = {
	CLK_LIST(gcc_usb30_sleep_clk),
	CLK_LIST(gcc_usb3_phy_aux_clk),
	CLK_LIST(gcc_usb3_phy_pipe_clk),
	CLK_LIST(gcc_usb3phy_phy_reset),
	CLK_LIST(gcc_usb_hs_ahb_clk),
	CLK_LIST(gcc_usb_hs_system_clk),
	CLK_LIST(gcc_usb_phy_cfg_ahb2phy_clk),
+1 −0
Original line number Diff line number Diff line
@@ -246,6 +246,7 @@
#define clk_gcc_usb30_sleep_clk 0xd0b65c92
#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0
#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2
#define clk_gcc_usb3phy_phy_reset 0xb1a4f885
#define clk_gcc_usb_hs_ahb_clk 0x72ce8032
#define clk_gcc_usb_hs_system_clk 0xa11972e5
#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e