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Commit 301860d5 authored by Rohit Vaswani's avatar Rohit Vaswani
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ARM: dts: msm: Enable Single Bit cache error interrupt and polling for 8992 



Add the single bit error interrupt and the polling delay to detect
single-bit errors in L1 and L2 for MSM8992.

Change-Id: Ie76fc09e7caae9debe1c7a726306f8eddc62a2f4
Signed-off-by: default avatarRohit Vaswani <rvaswani@codeaurora.org>
parent c22e2d9e
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