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Commit 2ef97f6f authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add DT entries for SATA controller and PHY on MPQ8092"

parents b9a05a13 caf9c2d5

arch/arm/boot/dts/qcom/mpq8092-cdp.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -66,6 +66,14 @@ 
	status = "ok";

};



&sataphy0 {

	status = "ok";

};



&sata0 {

	status = "ok";

};



&sdhc_1 {

	vdd-supply = <&pma8084_l20>;

	qcom,vdd-voltage-level = <2950000 2950000>;

arch/arm/boot/dts/qcom/mpq8092.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -1018,6 +1018,33 @@ 
		qcom,vreg-0.9-voltage-level = <950000 950000 24000>;

	};



	sataphy0: sataphy@0xfc581000 {

		compatible = "qcom,sataphy";

		reg = <0xfc581000 0x400>;

		reg-names = "phy_mem";

		#phy-cells = <0>;

		vdda-phy-supply = <&pma8084_l19>;

		vdda-pll-supply = <&pma8084_l22>;

		vdda-phy-max-microamp = <50000>;

		vdda-pll-max-microamp = <12000>;



		status = "disabled";

	};



	sata0: sata@0xfc580000 {

		compatible = "qcom,msm-ahci";

		reg = <0xfc580000 0x400>;

		interrupts = <0 292 0>;



		phys = <&sataphy0>;

		phy-names = "sata-6g";

		clock-names = "core_clk", "iface_clk", "pmalive_clk",

				"rxoob_clk", "asic0_clk", "rbc0_clk";

		max-clock-frequency-hz = <0 0 100000000

					100000000 300000000 300000000>;

		status = "disabled";

	};



	qcom,wdt@f9017000 {

		compatible = "qcom,msm-watchdog";

		reg = <0xf9017000 0x1000>;