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Commit caf9c2d5 authored by Sujit Reddy Thumma's avatar Sujit Reddy Thumma Committed by Venkat Gopalakrishnan
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ARM: dts: msm: Add DT entries for SATA controller and PHY on MPQ8092 



Add AHCI SATA controller and MSM SATA PHY nodes for MPQ8092.
This adds support for external SATA drives that are powered from
external power supply.

Change-Id: I988ec20498f0371f92137651740a67a99dffd040
Signed-off-by: default avatarSujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
parent 5471a014

arch/arm/boot/dts/qcom/mpq8092-cdp.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -66,6 +66,14 @@ 
	status = "ok";

};



&sataphy0 {

	status = "ok";

};



&sata0 {

	status = "ok";

};



&sdhc_1 {

	vdd-supply = <&pma8084_l20>;

	qcom,vdd-voltage-level = <2950000 2950000>;

arch/arm/boot/dts/qcom/mpq8092.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -570,6 +570,33 @@ 
		qcom,vreg-0.9-voltage-level = <950000 950000 24000>;

	};



	sataphy0: sataphy@0xfc581000 {

		compatible = "qcom,sataphy";

		reg = <0xfc581000 0x400>;

		reg-names = "phy_mem";

		#phy-cells = <0>;

		vdda-phy-supply = <&pma8084_l19>;

		vdda-pll-supply = <&pma8084_l22>;

		vdda-phy-max-microamp = <50000>;

		vdda-pll-max-microamp = <12000>;



		status = "disabled";

	};



	sata0: sata@0xfc580000 {

		compatible = "qcom,msm-ahci";

		reg = <0xfc580000 0x400>;

		interrupts = <0 292 0>;



		phys = <&sataphy0>;

		phy-names = "sata-6g";

		clock-names = "core_clk", "iface_clk", "pmalive_clk",

				"rxoob_clk", "asic0_clk", "rbc0_clk";

		max-clock-frequency-hz = <0 0 100000000

					100000000 300000000 300000000>;

		status = "disabled";

	};



	qcom,wdt@f9017000 {

		compatible = "qcom,msm-watchdog";

		reg = <0xf9017000 0x1000>;