Loading arch/arm/boot/dts/qcom/fsm9900-cdp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -50,6 +50,10 @@ qcom,ext-ref-clk; status = "ok"; }; qcom,danipc@251f8000 { status = "ok"; }; }; &sdhc_1 { Loading arch/arm/boot/dts/qcom/fsm9900-mtp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,10 @@ qcom,ep-latency = <1000>; status = "ok"; }; qcom,danipc@251f8000 { status = "ok"; }; }; &sdhc_1 { Loading arch/arm/boot/dts/qcom/fsm9900.dtsi +25 −0 Original line number Diff line number Diff line Loading @@ -1729,6 +1729,31 @@ reg-names = "wallclock_time_bank", "wallclock_cntrl_bank"; reg = <0xfd4aa000 0x20>, <0xfd4a9000 0x40>; }; qcom,danipc@251f8000 { compatible = "qcom,danipc"; reg-names = "ipc_bufs", "agent_table", "krait_ipc_intr_en", "cpu0_ipc", "cpu1_ipc", "cpu2_ipc", "cpu3_ipc", "dsp0_ipc", "dsp1_ipc", "dsp2_ipc", "krait_ipc", "qdsp6_0_ipc", "qdsp6_1_ipc", "qdsp6_2_ipc", "qdsp6_3_ipc"; reg = <0x251f8000 0x8000>, /* ipc_bufs */ <0xf601ac00 0x2000>, /* agent_table */ <0xfd4a3500 0x100>, /* krait_ipc_intr_en */ <0xf683a000 0x100>, /* cpu0_ipc */ <0xf683a000 0x100>, /* cpu1_ipc */ <0xf683c000 0x100>, /* cpu2_ipc */ <0xf683c000 0x100>, /* cpu3_ipc */ <0xf6862000 0x100>, /* dsp0_ipc */ <0xf6862000 0x100>, /* dsp1_ipc */ <0xf6878000 0x100>, /* dsp2_ipc */ <0xfd490000 0x100>, /* krait_ipc */ <0xfd491000 0x100>, /* qdsp6_0_ipc */ <0xfd492000 0x100>, /* qdsp6_1_ipc */ <0xfd493000 0x100>, /* qdsp6_2_ipc */ <0xfd494000 0x100>; /* qdsp6_3_ipc */ interrupts = <0 202 0>; }; }; &gdsc_pcie_0{ Loading Loading
arch/arm/boot/dts/qcom/fsm9900-cdp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -50,6 +50,10 @@ qcom,ext-ref-clk; status = "ok"; }; qcom,danipc@251f8000 { status = "ok"; }; }; &sdhc_1 { Loading
arch/arm/boot/dts/qcom/fsm9900-mtp.dtsi +4 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,10 @@ qcom,ep-latency = <1000>; status = "ok"; }; qcom,danipc@251f8000 { status = "ok"; }; }; &sdhc_1 { Loading
arch/arm/boot/dts/qcom/fsm9900.dtsi +25 −0 Original line number Diff line number Diff line Loading @@ -1729,6 +1729,31 @@ reg-names = "wallclock_time_bank", "wallclock_cntrl_bank"; reg = <0xfd4aa000 0x20>, <0xfd4a9000 0x40>; }; qcom,danipc@251f8000 { compatible = "qcom,danipc"; reg-names = "ipc_bufs", "agent_table", "krait_ipc_intr_en", "cpu0_ipc", "cpu1_ipc", "cpu2_ipc", "cpu3_ipc", "dsp0_ipc", "dsp1_ipc", "dsp2_ipc", "krait_ipc", "qdsp6_0_ipc", "qdsp6_1_ipc", "qdsp6_2_ipc", "qdsp6_3_ipc"; reg = <0x251f8000 0x8000>, /* ipc_bufs */ <0xf601ac00 0x2000>, /* agent_table */ <0xfd4a3500 0x100>, /* krait_ipc_intr_en */ <0xf683a000 0x100>, /* cpu0_ipc */ <0xf683a000 0x100>, /* cpu1_ipc */ <0xf683c000 0x100>, /* cpu2_ipc */ <0xf683c000 0x100>, /* cpu3_ipc */ <0xf6862000 0x100>, /* dsp0_ipc */ <0xf6862000 0x100>, /* dsp1_ipc */ <0xf6878000 0x100>, /* dsp2_ipc */ <0xfd490000 0x100>, /* krait_ipc */ <0xfd491000 0x100>, /* qdsp6_0_ipc */ <0xfd492000 0x100>, /* qdsp6_1_ipc */ <0xfd493000 0x100>, /* qdsp6_2_ipc */ <0xfd494000 0x100>; /* qdsp6_3_ipc */ interrupts = <0 202 0>; }; }; &gdsc_pcie_0{ Loading