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Commit e496fc5d authored by Venkatesh Yadav Abbarapu's avatar Venkatesh Yadav Abbarapu Committed by Gilad Avidov
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ARM: dts: qcom: add danipc nodes for fsm9900 



Add d/t entries for all ipc edges in FSM9900 targets.

Change-Id: I687216ee4f3b40b1bdbbcfd89401c6c35ef27da0
Acked-by: default avatarVladik Goytin <c_vgoyti@qti.qualcomm.com>
Signed-off-by: default avatarVenkatesh Yadav Abbarapu <quicvenkat@codeaurora.org>
parent d50d111c

arch/arm/boot/dts/qcom/fsm9900-cdp.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -50,6 +50,10 @@ 
		qcom,ext-ref-clk;

		status = "ok";

	};



	qcom,danipc@251f8000 {

		status = "ok";

	};

};



&sdhc_1 {

arch/arm/boot/dts/qcom/fsm9900-mtp.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -54,6 +54,10 @@ 
		qcom,ep-latency = <1000>;

		status = "ok";

	};



	qcom,danipc@251f8000 {

		status = "ok";

	};

};



&sdhc_1 {

arch/arm/boot/dts/qcom/fsm9900.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -1729,6 +1729,31 @@ 
		reg-names = "wallclock_time_bank", "wallclock_cntrl_bank";

		reg = <0xfd4aa000 0x20>, <0xfd4a9000 0x40>;

	};



	qcom,danipc@251f8000 {

		compatible = "qcom,danipc";

		reg-names = "ipc_bufs", "agent_table", "krait_ipc_intr_en",

				"cpu0_ipc", "cpu1_ipc", "cpu2_ipc", "cpu3_ipc",

				"dsp0_ipc", "dsp1_ipc", "dsp2_ipc", "krait_ipc",

				"qdsp6_0_ipc", "qdsp6_1_ipc", "qdsp6_2_ipc",

				"qdsp6_3_ipc";

		reg = <0x251f8000 0x8000>, /* ipc_bufs */

			<0xf601ac00 0x2000>, /* agent_table */

			<0xfd4a3500 0x100>, /* krait_ipc_intr_en */

			<0xf683a000 0x100>, /* cpu0_ipc */

			<0xf683a000 0x100>, /* cpu1_ipc */

			<0xf683c000 0x100>, /* cpu2_ipc */

			<0xf683c000 0x100>, /* cpu3_ipc */

			<0xf6862000 0x100>, /* dsp0_ipc */

			<0xf6862000 0x100>, /* dsp1_ipc */

			<0xf6878000 0x100>, /* dsp2_ipc */

			<0xfd490000 0x100>, /* krait_ipc */

			<0xfd491000 0x100>, /* qdsp6_0_ipc */

			<0xfd492000 0x100>, /* qdsp6_1_ipc */

			<0xfd493000 0x100>, /* qdsp6_2_ipc */

			<0xfd494000 0x100>; /* qdsp6_3_ipc */

		interrupts = <0 202 0>;

	};

};



&gdsc_pcie_0{