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Commit 26b6426e authored by Shubhraprakash Das's avatar Shubhraprakash Das
Browse files

msm: kgsl: Read fault register on ringbuffer h/w fault 



Read the CP_HW_FAULT register which gives more information
about the fault when ringbuffer h/w fault interrupt is
generated. Also, limit the printing of this interrupt to
prevent watchdog timeout.

Change-Id: I8eba72ab50553e72f733034c7fa0ea3ca69db343
CRs-Fixed: 613940
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent 36b9697e

drivers/gpu/msm/a4xx_reg.h

+2 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -432,6 +432,7 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_CP_PROTECT_CTRL		0x250

#define A4XX_CP_ME_STATUS		0x4D1

#define A4XX_CP_WFI_PEND_CTR		0x4d2

#define A4XX_CP_HW_FAULT		0x4D8

#define A4XX_CP_PERFCTR_CP_SEL_0	0x500

#define A4XX_CP_PERFCTR_CP_SEL_1	0x501

#define A4XX_CP_SCRATCH_REG0		0x578

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ enum adreno_regs { 
	ADRENO_REG_CP_MERCIU_DATA2,

	ADRENO_REG_CP_MEQ_ADDR,

	ADRENO_REG_CP_MEQ_DATA,

	ADRENO_REG_CP_HW_FAULT,

	ADRENO_REG_SCRATCH_ADDR,

	ADRENO_REG_SCRATCH_UMSK,

	ADRENO_REG_SCRATCH_REG2,

drivers/gpu/msm/adreno_a3xx.c

+7 −2
Original line number Diff line number Diff line
@@ -773,9 +773,13 @@ void a3xx_a4xx_err_callback(struct adreno_device *adreno_dev, int bit) 
		KGSL_DRV_CRIT_RATELIMIT(device,

				"ringbuffer reserved bit error interrupt\n");

		break;

	case A3XX_INT_CP_HW_FAULT:

		KGSL_DRV_CRIT(device, "ringbuffer hardware fault\n");

	case A3XX_INT_CP_HW_FAULT: {

		unsigned int reg;

		adreno_readreg(adreno_dev, ADRENO_REG_CP_HW_FAULT, &reg);

		KGSL_DRV_CRIT_RATELIMIT(device,

			"CP | Ringbuffer HW fault | status=%x\n", reg);

		break;

	}

	case A3XX_INT_CP_REG_PROTECT_FAULT: {

		unsigned int reg;

		kgsl_regread(device, A3XX_CP_PROTECT_STATUS, &reg);
@@ -2217,6 +2221,7 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_MERCIU_DATA2, A3XX_CP_MERCIU_DATA2),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A3XX_CP_MEQ_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A3XX_CP_MEQ_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A3XX_CP_HW_FAULT),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A3XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A3XX_RBBM_PERFCTR_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,

drivers/gpu/msm/adreno_a4xx.c

+1 −0
Original line number Diff line number Diff line
@@ -563,6 +563,7 @@ static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_MERCIU_DATA2, A4XX_CP_MERCIU_DATA2),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A4XX_CP_MEQ_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A4XX_CP_MEQ_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A4XX_CP_HW_FAULT),

	ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_ADDR, A4XX_CP_SCRATCH_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_SCRATCH_UMSK, A4XX_CP_SCRATCH_UMASK),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A4XX_RBBM_STATUS),