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Commit 36b9697e authored by Shubhraprakash Das's avatar Shubhraprakash Das
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msm: kgsl: Flush the UCHE when context changes



Add commands to flush the GPU UCHE when a new context submits
commands to GPU. The ensures that the new context does not use
stale data present in UCHE.

Change-Id: I123a323be5f3fb9d1f9f96fed5bb68b8d0d27d76
CRs-Fixed: 607976
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent 816351dd
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+1 −0
Original line number Diff line number Diff line
@@ -356,6 +356,7 @@ enum adreno_regs {
	ADRENO_REG_SQ_INST_STORE_MANAGMENT,
	ADRENO_REG_TP0_CHICKEN,
	ADRENO_REG_RBBM_RBBM_CTL,
	ADRENO_REG_UCHE_INVALIDATE0,
	ADRENO_REG_REGISTER_MAX,
};

+2 −0
Original line number Diff line number Diff line
@@ -2265,6 +2265,8 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
	ADRENO_REG_DEFINE(ADRENO_REG_TP0_CHICKEN, A3XX_TP0_CHICKEN),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_RBBM_CTL, A3XX_RBBM_RBBM_CTL),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A3XX_RBBM_SW_RESET_CMD),
	ADRENO_REG_DEFINE(ADRENO_REG_UCHE_INVALIDATE0,
			A3XX_UCHE_CACHE_INVALIDATE0_REG),
};

const struct adreno_reg_offsets a3xx_reg_offsets = {
+2 −1
Original line number Diff line number Diff line
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -607,6 +607,7 @@ static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
				A4XX_SP_FS_OBJ_START),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_RBBM_CTL, A4XX_RBBM_RBBM_CTL),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A4XX_RBBM_SW_RESET_CMD),
	ADRENO_REG_DEFINE(ADRENO_REG_UCHE_INVALIDATE0, A4XX_UCHE_INVALIDATE0),
};

const struct adreno_reg_offsets a4xx_reg_offsets = {
+10 −2
Original line number Diff line number Diff line
@@ -503,7 +503,7 @@ static int adreno_context_restore(struct adreno_device *adreno_dev,
				  struct adreno_context *context)
{
	struct kgsl_device *device;
	unsigned int cmds[5];
	unsigned int cmds[8];

	if (adreno_dev == NULL || context == NULL)
		return -EINVAL;
@@ -517,8 +517,16 @@ static int adreno_context_restore(struct adreno_device *adreno_dev,
	cmds[3] = device->memstore.gpuaddr +
		KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL, current_context);
	cmds[4] = context->base.id;
	/* Flush the UCHE for new context */
	cmds[5] = cp_type0_packet(
		adreno_getreg(adreno_dev, ADRENO_REG_UCHE_INVALIDATE0), 2);
	cmds[6] = 0;
	if (adreno_is_a4xx(adreno_dev))
		cmds[7] = 0x12;
	else if (adreno_is_a3xx(adreno_dev))
		cmds[7] = 0x90000000;
	return adreno_ringbuffer_issuecmds(device, context,
				KGSL_CMD_FLAGS_NONE, cmds, 5);
				KGSL_CMD_FLAGS_NONE, cmds, 8);
}

/**