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Commit 25a1ac21 authored by Sachin Shah's avatar Sachin Shah
Browse files

msm: vidc: Enable venus power management



Besides clock gating, turn venus core power off
if the core stays idle for given amount of time.
Powering off venus core involves telling TZ to
suspend venus core, detach IOMMU, disable GDSC
regulator, unvote DDR/OCMEM buses.

Turn it on again when driver starts processing new
commands before enabling clocks.

Protect clock and power states and operations
with a common lock.

Change-Id: I49654069920ddaae0e2f8792b14cd1bfeb431c34
Signed-off-by: default avatarSachin Shah <sachins@codeaurora.org>
parent 246c5ae7
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+1 −0
Original line number Diff line number Diff line
@@ -1170,6 +1170,7 @@ u32 hfi_process_msg_packet(
					msg_hdr);
		break;
	case HFI_MSG_SYS_IDLE:
	case HFI_MSG_SYS_PC_PREP_DONE:
		break;
	case HFI_MSG_SYS_SESSION_INIT_DONE:
		SANITIZE_SESSION_PKT(msg_hdr);
+634 −274

File changed.

Preview size limit exceeded, changes collapsed.

+6 −2
Original line number Diff line number Diff line
@@ -182,12 +182,14 @@ struct venus_hfi_device {
	struct list_head sess_head;
	u32 intr_status;
	u32 device_id;
	u32 load;
	u32 clk_load;
	u32 bus_load[MSM_VIDC_MAX_DEVICES];
	u32 clocks_enabled;
	u32 power_enabled;
	enum vidc_clocks clk_gating_level;
	struct mutex read_lock;
	struct mutex write_lock;
	struct mutex clock_lock;
	struct mutex clk_pwr_lock;
	struct mutex session_lock;
	msm_vidc_callback callback;
	struct vidc_mem_addr iface_q_table;
@@ -198,6 +200,7 @@ struct venus_hfi_device {
	struct smem_client *hal_client;
	struct hal_data *hal_data;
	struct workqueue_struct *vidc_workq;
	struct workqueue_struct *venus_pm_workq;
	int spur_count;
	int reg_count;
	u32 base_addr;
@@ -206,6 +209,7 @@ struct venus_hfi_device {
	u32 irq;
	struct venus_resources resources;
	struct msm_vidc_platform_resources *res;
	struct regulator *gdsc;
};

void venus_hfi_delete_device(void *device);
+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_SHFT	0x1
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_BMSK	0x1
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_SHFT	0x0
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY           0x100
#define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK     0x40000000

/* HFI_QTBL_INFO */