Loading drivers/clk/qcom/clock-pll.c +3 −0 Original line number Diff line number Diff line Loading @@ -496,6 +496,9 @@ static long variable_rate_pll_round_rate(struct clk *c, unsigned long rate) if (!pll->src_rate) return 0; if (pll->no_prepared_reconfig && c->prepare_count && c->rate != rate) return -EINVAL; if (rate < pll->min_rate) rate = pll->min_rate; if (rate > pll->max_rate) Loading include/soc/qcom/clock-pll.h +2 −0 Original line number Diff line number Diff line Loading @@ -121,6 +121,7 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *c) * @masks: masks used for settings in config_reg * @vals: configuration values to be written to PLL registers * @freq_tbl: pll freq table * @no_prepared_reconfig: Fail round_rate if pll is prepared * @c: clk * @base: pointer to base address of ioremapped registers. */ Loading Loading @@ -148,6 +149,7 @@ struct pll_clk { unsigned long max_rate; bool inited; bool no_prepared_reconfig; struct clk c; void *const __iomem *base; Loading Loading
drivers/clk/qcom/clock-pll.c +3 −0 Original line number Diff line number Diff line Loading @@ -496,6 +496,9 @@ static long variable_rate_pll_round_rate(struct clk *c, unsigned long rate) if (!pll->src_rate) return 0; if (pll->no_prepared_reconfig && c->prepare_count && c->rate != rate) return -EINVAL; if (rate < pll->min_rate) rate = pll->min_rate; if (rate > pll->max_rate) Loading
include/soc/qcom/clock-pll.h +2 −0 Original line number Diff line number Diff line Loading @@ -121,6 +121,7 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *c) * @masks: masks used for settings in config_reg * @vals: configuration values to be written to PLL registers * @freq_tbl: pll freq table * @no_prepared_reconfig: Fail round_rate if pll is prepared * @c: clk * @base: pointer to base address of ioremapped registers. */ Loading Loading @@ -148,6 +149,7 @@ struct pll_clk { unsigned long max_rate; bool inited; bool no_prepared_reconfig; struct clk c; void *const __iomem *base; Loading
