iommu: msm: Workaround for SMMU PTE prefetch HW bug

Some SMMU implementation has speculative pre-fetch to
optimize performance by reducing HTW to DDR. MMU-500
also implements such pre-fetching with a limitation
that it cannot identify when to stop pre-fetching.
This results into pre-fetching junk data after the
last PTE from last level of page table. This junk PTE
can result into any SMMU issues like incorrect
translation, permission fault, page fault etc.

Now, to avoid that, we anyway do memset 0 to the entire
page allocated to page table. But we flush only those
entries to DDR which are part of valid mapping. Any
data after the valid page table entries may not be
set to zero as we don't issue explicit flush for them.
And this results into the problem described above.

Do an explicit flush for few guard page table entries
and make sure that they reflect 0 in DDR. This stops
SMMU to do over pre-fetch.

CRs-Fixed: 644219
Change-Id: I4695e50e14d6122356090118e15311797ad5e290
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>