Merge "qcom: clock-cpu-8994: Add lock bit masks" (21aa024a) · Commits · e / devices / android_kernel_sony_msm8994

drivers/clk/qcom/clock-cpu-8994.c

+8 −4

Original line number	Diff line number	Diff line
		@@ -148,7 +148,7 @@ static struct pll_clk a57_pll0 = {
		.alpha_reg = (void __iomem *)C1_PLL_ALPHA,
		.config_reg = (void __iomem *)C1_PLL_USER_CTL,
		.config_ctl_reg = (void __iomem *)C1_PLL_CONFIG_CTL,
		.status_reg = (void __iomem *)C1_PLL_STATUS,
		.status_reg = (void __iomem *)C1_PLL_MODE,
		.masks = {
		.pre_div_mask = BIT(12),
		.post_div_mask = BM(9, 8),
		@@ -156,6 +156,7 @@ static struct pll_clk a57_pll0 = {
		.main_output_mask = BIT(0),
		.early_output_mask = BIT(3),
		.apc_pdn_mask = BIT(24),
		.lock_mask = BIT(31),
		},
		.vals = {
		.post_div_masked = 0x100,
		@@ -180,7 +181,7 @@ static struct pll_clk a57_pll1 = {
		.alpha_reg = (void __iomem *)C1_PLLA_ALPHA,
		.config_reg = (void __iomem *)C1_PLLA_USER_CTL,
		.config_ctl_reg = (void __iomem *)C1_PLLA_CONFIG_CTL,
		.status_reg = (void __iomem *)C1_PLLA_STATUS,
		.status_reg = (void __iomem *)C1_PLLA_MODE,
		.masks = {
		.pre_div_mask = BIT(12),
		.post_div_mask = BM(9, 8),
		@@ -188,6 +189,7 @@ static struct pll_clk a57_pll1 = {
		.main_output_mask = BIT(0),
		.early_output_mask = BIT(3),
		.apc_pdn_mask = BIT(24),
		.lock_mask = BIT(31),
		},
		.vals = {
		.post_div_masked = 0x300,
		@@ -214,7 +216,7 @@ static struct pll_clk a53_pll0 = {
		.alpha_reg = (void __iomem *)C0_PLL_ALPHA,
		.config_reg = (void __iomem *)C0_PLL_USER_CTL,
		.config_ctl_reg = (void __iomem *)C0_PLL_CONFIG_CTL,
		.status_reg = (void __iomem *)C0_PLL_STATUS,
		.status_reg = (void __iomem *)C0_PLL_MODE,
		.masks = {
		.pre_div_mask = BIT(12),
		.post_div_mask = BM(9, 8),
		@@ -222,6 +224,7 @@ static struct pll_clk a53_pll0 = {
		.main_output_mask = BIT(0),
		.early_output_mask = BIT(3),
		.apc_pdn_mask = BIT(24),
		.lock_mask = BIT(31),
		},
		.vals = {
		.post_div_masked = 0x100,
		@@ -246,7 +249,7 @@ static struct pll_clk a53_pll1 = {
		.alpha_reg = (void __iomem *)C0_PLLA_ALPHA,
		.config_reg = (void __iomem *)C0_PLLA_USER_CTL,
		.config_ctl_reg = (void __iomem *)C0_PLLA_CONFIG_CTL,
		.status_reg = (void __iomem *)C0_PLLA_STATUS,
		.status_reg = (void __iomem *)C0_PLLA_MODE,
		.masks = {
		.pre_div_mask = BIT(12),
		.post_div_mask = BM(9, 8),
		@@ -254,6 +257,7 @@ static struct pll_clk a53_pll1 = {
		.main_output_mask = BIT(0),
		.early_output_mask = BIT(3),
		.apc_pdn_mask = BIT(24),
		.lock_mask = BIT(31),
		},
		.vals = {
		.post_div_masked = 0x300,