Merge "qcom: clock-pll: Add support for different lock masks" (64010b26) · Commits · e / devices / android_kernel_sony_msm8994

drivers/clk/qcom/clock-pll.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -166,6 +166,7 @@ static int sr2_pll_clk_enable(struct clk *c)
		struct pll_clk *pll = to_pll_clk(c);
		int ret = 0, count;
		u32 mode = readl_relaxed(PLL_MODE_REG(pll));
		u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;

		spin_lock_irqsave(&pll_reg_lock, flags);

		@@ -189,12 +190,12 @@ static int sr2_pll_clk_enable(struct clk *c)

		/* Wait for pll to lock. */
		for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
		if (readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT)
		if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)
		break;
		udelay(1);
		}

		if (!(readl_relaxed(PLL_STATUS_REG(pll)) & PLL_LOCKED_BIT))
		if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask))
		pr_err("PLL %s didn't lock after enabling it!\n", c->dbg_name);

		/* Enable PLL output. */

+2 −0

Original line number	Diff line number	Diff line
		@@ -45,6 +45,7 @@ struct pll_freq_tbl {
		* @mn_en_mask: ORed with pll config register to enable the mn counter
		* @main_output_mask: ORed with pll config register to enable the main output
		* @apc_pdn_mask: ORed with pll config register to enable/disable APC PDN
		* @lock_mask: Mask that indicates that the PLL has locked
		*/
		struct pll_config_masks {
		u32 apc_pdn_mask;
		@@ -54,6 +55,7 @@ struct pll_config_masks {
		u32 mn_en_mask;
		u32 main_output_mask;
		u32 early_output_mask;
		u32 lock_mask;
		};

		struct pll_config_vals {