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Commit 1e741ff7 authored by Xiaogang Cui's avatar Xiaogang Cui
Browse files

ARM: dts: msm: Add CTI devices of processors for 8939 



Add CoreSight CTI devices to device tree to allow
CoreSight CTI driver to manage them.

Change-Id: I566082442e1c32d19552a7ff1e5982c8a6f683ee
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 60ce268f

arch/arm/boot/dts/qcom/msm8939-coresight.dtsi

+296 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;
@@ -59,6 +60,7 @@ 
		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;
@@ -110,4 +112,298 @@ 
		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;

	};



	cti0: cti@810000 {

		compatible = "arm,coresight-cti";

		reg = <0x810000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <6>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti1: cti@811000 {

		compatible = "arm,coresight-cti";

		reg = <0x811000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <7>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti2: cti@812000 {

		compatible = "arm,coresight-cti";

		reg = <0x812000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <8>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti3: cti@813000 {

		compatible = "arm,coresight-cti";

		reg = <0x813000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <9>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti4: cti@814000 {

		compatible = "arm,coresight-cti";

		reg = <0x814000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <10>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti5: cti@815000 {

		compatible = "arm,coresight-cti";

		reg = <0x815000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <11>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti6: cti@816000 {

		compatible = "arm,coresight-cti";

		reg = <0x816000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <12>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti7: cti@817000 {

		compatible = "arm,coresight-cti";

		reg = <0x817000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <13>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti8: cti@818000 {

		compatible = "arm,coresight-cti";

		reg = <0x818000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <14>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_perf_cpu0: cti@8f8000 {

		compatible = "arm,coresight-cti";

		reg = <0x8f8000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-name = "coresight-cti-perf-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_perf_cpu1: cti@8f9000 {

		compatible = "arm,coresight-cti";

		reg = <0x8f9000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-name = "coresight-cti-perf-cpu1";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_perf_cpu2: cti@8fa000 {

		compatible = "arm,coresight-cti";

		reg = <0x8fa000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <17>;

		coresight-name = "coresight-cti-perf-cpu2";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_perf_cpu3: cti@8fb000 {

		compatible = "arm,coresight-cti";

		reg = <0x8fb000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <18>;

		coresight-name = "coresight-cti-perf-cpu3";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_pow_cpu0: cti@8d8000 {

		compatible = "arm,coresight-cti";

		reg = <0x8d8000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <19>;

		coresight-name = "coresight-cti-pow-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_pow_cpu1: cti@8d9000 {

		compatible = "arm,coresight-cti";

		reg = <0x8d9000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <20>;

		coresight-name = "coresight-cti-pow-cpu1";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_pow_cpu2: cti@8da000 {

		compatible = "arm,coresight-cti";

		reg = <0x8da000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <21>;

		coresight-name = "coresight-cti-pow-cpu2";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_pow_cpu3: cti@8db000 {

		compatible = "arm,coresight-cti";

		reg = <0x8db000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <22>;

		coresight-name = "coresight-cti-pow-cpu3";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_rpm_cpu0: cti@83c000 {

		compatible = "arm,coresight-cti";

		reg = <0x83c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <23>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_modem_cpu0: cti@838000 {

		compatible = "arm,coresight-cti";

		reg = <0x838000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <24>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_wcn_cpu0: cti@835000 {

		compatible = "arm,coresight-cti";

		reg = <0x835000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-name = "coresight-cti-wcn-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	cti_video_cpu0: cti@830000 {

		compatible = "arm,coresight-cti";

		reg = <0x830000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <26>;

		coresight-name = "coresight-cti-video-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

};