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Commit 60ce268f authored by Xiaogang Cui's avatar Xiaogang Cui Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add coresight byte counter interrupt for 8939 



Add device tree entry to support CoreSight byte counter interrupt
feature which raises an interrupt on transfer of programmed
number of bytes to ETR-memory.

Change-Id: Id518e0bdadd1e156d009aa8d186ad376a53b5e24
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 77e05d02

arch/arm/boot/dts/qcom/msm8939-coresight.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
		reg = <0x826000 0x1000>,

		      <0x884000 0x15000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 166 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;