clk: qcom: clock-pll: Increase delay for "transient" PLL locks

According to the new recommendation, the explicit delay before
the initial check for the PLL lock bit for the four Veyron PLLs
on MSM8992/MSM8994 needs to be 200us instead of 50us. Increase
the explicit delay to 200us before checking if the PLL lock bit
is set.

Change-Id: Ie5f1d7571604ab667c7840d07153d6bdd5bb0e08
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>