Loading drivers/clk/qcom/clock-gcc-8994.c +12 −0 Original line number Diff line number Diff line Loading @@ -85,6 +85,7 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); #define USB_HS_SYSTEM_CMD_RCGR (0x0490) #define USB2_HS_PHY_BCR (0x04A8) #define USB2_HS_PHY_SLEEP_CBCR (0x04AC) #define QUSB2_PHY_BCR (0x04B8) #define USB_PHY_CFG_AHB2PHY_CBCR (0x1A84) #define SDCC1_APPS_CMD_RCGR (0x04D0) #define SDCC1_APPS_CBCR (0x04C4) Loading Loading @@ -1359,6 +1360,16 @@ static struct rcg_clk usb_hs_system_clk_src = { }, }; static struct reset_clk gcc_qusb2_phy_reset = { .reset_reg = QUSB2_PHY_BCR, .base = &virt_base, .c = { .dbg_name = "gcc_qusb2_phy_reset", .ops = &clk_ops_rst, CLK_INIT(gcc_qusb2_phy_reset.c), }, }; static struct reset_clk gcc_usb3_phy_reset = { .reset_reg = USB3_PHY_BCR, .base = &virt_base, Loading Loading @@ -2678,6 +2689,7 @@ static struct clk_lookup msm_clocks_gcc_8994[] = { CLK_LIST(usb30_mock_utmi_clk_src), CLK_LIST(usb3_phy_aux_clk_src), CLK_LIST(usb_hs_system_clk_src), CLK_LIST(gcc_qusb2_phy_reset), CLK_LIST(gcc_usb3_phy_reset), CLK_LIST(gcc_usb3phy_phy_reset), CLK_LIST(gpll0_out_mmsscc), Loading include/dt-bindings/clock/msm-clocks-8994.h +1 −0 Original line number Diff line number Diff line Loading @@ -155,6 +155,7 @@ #define clk_usb30_mock_utmi_clk_src 0xa024a976 #define clk_usb3_phy_aux_clk_src 0x15eec63c #define clk_usb_hs_system_clk_src 0x28385546 #define clk_gcc_qusb2_phy_reset 0x3ce5fa84 #define clk_gcc_usb3_phy_reset 0x03d559f1 #define clk_gcc_usb3phy_phy_reset 0xb1a4f885 #define clk_gpll0_out_mmsscc 0x0ded70aa Loading Loading
drivers/clk/qcom/clock-gcc-8994.c +12 −0 Original line number Diff line number Diff line Loading @@ -85,6 +85,7 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); #define USB_HS_SYSTEM_CMD_RCGR (0x0490) #define USB2_HS_PHY_BCR (0x04A8) #define USB2_HS_PHY_SLEEP_CBCR (0x04AC) #define QUSB2_PHY_BCR (0x04B8) #define USB_PHY_CFG_AHB2PHY_CBCR (0x1A84) #define SDCC1_APPS_CMD_RCGR (0x04D0) #define SDCC1_APPS_CBCR (0x04C4) Loading Loading @@ -1359,6 +1360,16 @@ static struct rcg_clk usb_hs_system_clk_src = { }, }; static struct reset_clk gcc_qusb2_phy_reset = { .reset_reg = QUSB2_PHY_BCR, .base = &virt_base, .c = { .dbg_name = "gcc_qusb2_phy_reset", .ops = &clk_ops_rst, CLK_INIT(gcc_qusb2_phy_reset.c), }, }; static struct reset_clk gcc_usb3_phy_reset = { .reset_reg = USB3_PHY_BCR, .base = &virt_base, Loading Loading @@ -2678,6 +2689,7 @@ static struct clk_lookup msm_clocks_gcc_8994[] = { CLK_LIST(usb30_mock_utmi_clk_src), CLK_LIST(usb3_phy_aux_clk_src), CLK_LIST(usb_hs_system_clk_src), CLK_LIST(gcc_qusb2_phy_reset), CLK_LIST(gcc_usb3_phy_reset), CLK_LIST(gcc_usb3phy_phy_reset), CLK_LIST(gpll0_out_mmsscc), Loading
include/dt-bindings/clock/msm-clocks-8994.h +1 −0 Original line number Diff line number Diff line Loading @@ -155,6 +155,7 @@ #define clk_usb30_mock_utmi_clk_src 0xa024a976 #define clk_usb3_phy_aux_clk_src 0x15eec63c #define clk_usb_hs_system_clk_src 0x28385546 #define clk_gcc_qusb2_phy_reset 0x3ce5fa84 #define clk_gcc_usb3_phy_reset 0x03d559f1 #define clk_gcc_usb3phy_phy_reset 0xb1a4f885 #define clk_gpll0_out_mmsscc 0x0ded70aa Loading