Loading arch/arm/boot/dts/qcom/msmzirc-pinctrl.dtsi +50 −0 Original line number Diff line number Diff line Loading @@ -43,5 +43,55 @@ }; }; spi0_active { /* MOSI, MISO, CLK */ qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>; qcom,num-grp-pins = <3>; qcom,pin-func = <1>; label = "spi0-active"; /* active state */ spi0_default: default { drive-strength = <12>; /* 12 MA */ bias-disable = <0>; /* No PULL */ }; }; spi0_suspend { /* MOSI, MISO, CLK */ qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>; qcom,num-grp-pins = <3>; qcom,pin-func = <0>; label = "spi0-suspend"; /* suspended state */ spi0_sleep: sleep { drive-strength = <2>; /* 2 MA */ bias-pull-down; /* pull down */ }; }; spi0_cs0_active { /* CS */ qcom,pins = <&gp 2>; qcom,num-grp-pins = <1>; qcom,pin-func = <1>; label = "spi0-cs0-active"; spi0_cs0_active: cs0_active { drive-strength = <2>; bias-disable = <0>; }; }; spi0_cs0_suspend { /* CS */ qcom,pins = <&gp 2>; qcom,num-grp-pins = <1>; qcom,pin-func = <0>; label = "spi0-cs0-suspend"; spi0_cs0_sleep: cs0_sleep { drive-strength = <2>; bias-disable = <0>; }; }; }; }; arch/arm/boot/dts/qcom/msmzirc-sim.dts +12 −0 Original line number Diff line number Diff line Loading @@ -27,3 +27,15 @@ pinctrl-0 = <&uart_console_sleep>; }; &spi_0 { ethernet-switch@0 { compatible = "simtec,ks8851"; interrupt-parent = <&msm_gpio>; reg = <0>; spi-max-frequency = <2400000>; interrupts = <88 0>; vdd-io-supply = <&spi_eth_vreg>; vdd-phy-supply = <&spi_eth_vreg>; rst-gpio = <&msm_gpio 89 0>; }; }; arch/arm/boot/dts/qcom/msmzirc.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,10 @@ <237 0x10000>, <238 0x10000>; interrupt-parent = <&intc>; aliases { spi0 = &spi_0; }; soc: soc { }; }; Loading Loading @@ -168,6 +172,29 @@ status = "disabled"; }; spi_0: spi@78b5000 { /* BLSP1 QUP1 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0x78b5000 0x600>, <0x7884000 0x23000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 95 0>, <0 238 0>; spi-max-frequency = <50000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_default &spi0_cs0_active>; pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>; clocks = <&clock_gcc 0x8caa5b4f>, <&clock_gcc 0x759a76b0>; clock-names = "iface_clk", "core_clk"; qcom,infinite-mode = <0>; qcom,use-pinctrl; qcom,ver-reg-exists; qcom,master-id = <86>; }; }; #include "msmzirc-regulator.dtsi" Loading
arch/arm/boot/dts/qcom/msmzirc-pinctrl.dtsi +50 −0 Original line number Diff line number Diff line Loading @@ -43,5 +43,55 @@ }; }; spi0_active { /* MOSI, MISO, CLK */ qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>; qcom,num-grp-pins = <3>; qcom,pin-func = <1>; label = "spi0-active"; /* active state */ spi0_default: default { drive-strength = <12>; /* 12 MA */ bias-disable = <0>; /* No PULL */ }; }; spi0_suspend { /* MOSI, MISO, CLK */ qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>; qcom,num-grp-pins = <3>; qcom,pin-func = <0>; label = "spi0-suspend"; /* suspended state */ spi0_sleep: sleep { drive-strength = <2>; /* 2 MA */ bias-pull-down; /* pull down */ }; }; spi0_cs0_active { /* CS */ qcom,pins = <&gp 2>; qcom,num-grp-pins = <1>; qcom,pin-func = <1>; label = "spi0-cs0-active"; spi0_cs0_active: cs0_active { drive-strength = <2>; bias-disable = <0>; }; }; spi0_cs0_suspend { /* CS */ qcom,pins = <&gp 2>; qcom,num-grp-pins = <1>; qcom,pin-func = <0>; label = "spi0-cs0-suspend"; spi0_cs0_sleep: cs0_sleep { drive-strength = <2>; bias-disable = <0>; }; }; }; };
arch/arm/boot/dts/qcom/msmzirc-sim.dts +12 −0 Original line number Diff line number Diff line Loading @@ -27,3 +27,15 @@ pinctrl-0 = <&uart_console_sleep>; }; &spi_0 { ethernet-switch@0 { compatible = "simtec,ks8851"; interrupt-parent = <&msm_gpio>; reg = <0>; spi-max-frequency = <2400000>; interrupts = <88 0>; vdd-io-supply = <&spi_eth_vreg>; vdd-phy-supply = <&spi_eth_vreg>; rst-gpio = <&msm_gpio 89 0>; }; };
arch/arm/boot/dts/qcom/msmzirc.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,10 @@ <237 0x10000>, <238 0x10000>; interrupt-parent = <&intc>; aliases { spi0 = &spi_0; }; soc: soc { }; }; Loading Loading @@ -168,6 +172,29 @@ status = "disabled"; }; spi_0: spi@78b5000 { /* BLSP1 QUP1 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0x78b5000 0x600>, <0x7884000 0x23000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 95 0>, <0 238 0>; spi-max-frequency = <50000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_default &spi0_cs0_active>; pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>; clocks = <&clock_gcc 0x8caa5b4f>, <&clock_gcc 0x759a76b0>; clock-names = "iface_clk", "core_clk"; qcom,infinite-mode = <0>; qcom,use-pinctrl; qcom,ver-reg-exists; qcom,master-id = <86>; }; }; #include "msmzirc-regulator.dtsi"