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Commit 14f991a7 authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Nicolas Ferre
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ARM: at91: Fix at91sam9g45 and at91cap9 reset 



As on the other sam9 we need to cleanly shutdown the DDRAM before rebooting.

On those SoC the SDRAM/DDRAM controller is different. So, the assembly code
ends up being not cleanly combined with previous at91sam9_alt_restart function.

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent e9f68b5c

arch/arm/mach-at91/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ config HAVE_AT91_USART5 
config AT91_SAM9_ALT_RESET

	bool



config AT91_SAM9G45_RESET

	bool



menu "Atmel AT91 System-on-Chip"



choice
@@ -97,6 +100,7 @@ config ARCH_AT91SAM9G45 
	select HAVE_FB_ATMEL

	select HAVE_NET_MACB

	select HAVE_AT91_DBGU1

	select AT91_SAM9G45_RESET



config ARCH_AT91CAP9

	bool "AT91CAP9"
@@ -105,6 +109,7 @@ config ARCH_AT91CAP9 
	select HAVE_FB_ATMEL

	select HAVE_NET_MACB

	select HAVE_AT91_DBGU1

	select AT91_SAM9G45_RESET



config ARCH_AT91X40

	bool "AT91x40"

arch/arm/mach-at91/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ obj- := 


obj-$(CONFIG_AT91_PMC_UNIT)	+= clock.o

obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o

obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o



# CPU-specific support

obj-$(CONFIG_ARCH_AT91RM9200)	+= at91rm9200.o at91rm9200_time.o at91rm9200_devices.o

arch/arm/mach-at91/at91cap9.c

+1 −7
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ 
#include <mach/cpu.h>

#include <mach/at91cap9.h>

#include <mach/at91_pmc.h>

#include <mach/at91_rstc.h>



#include "soc.h"

#include "generic.h"
@@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = { 
	}

};



static void at91cap9_restart(char mode, const char *cmd)

{

	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);

}



/* --------------------------------------------------------------------

 *  AT91CAP9 processor initialization

 * -------------------------------------------------------------------- */
@@ -338,7 +332,7 @@ static void __init at91cap9_ioremap_registers(void) 


static void __init at91cap9_initialize(void)

{

	arm_pm_restart = at91cap9_restart;

	arm_pm_restart = at91sam9g45_restart;

	at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);



	/* Register GPIO subsystem */

arch/arm/mach-at91/at91sam9g45.c

+0 −6
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
#include <asm/mach/map.h>

#include <mach/at91sam9g45.h>

#include <mach/at91_pmc.h>

#include <mach/at91_rstc.h>

#include <mach/cpu.h>



#include "soc.h"
@@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = { 
	}

};



static void at91sam9g45_restart(char mode, const char *cmd)

{

	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);

}



/* --------------------------------------------------------------------

 *  AT91SAM9G45 processor initialization

 * -------------------------------------------------------------------- */

arch/arm/mach-at91/at91sam9g45_reset.S

0 → 100644
+40 −0
Original line number Diff line number Diff line 
/*

 * reset AT91SAM9G45 as per errata

 *

 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>

 *

 * unless the SDRAM is cleanly shutdown before we hit the

 * reset register it can be left driving the data bus and

 * killing the chance of a subsequent boot from NAND

 *

 * GPLv2 Only

 */



#include <linux/linkage.h>

#include <mach/hardware.h>

#include <mach/at91sam9_ddrsdr.h>

#include <mach/at91_rstc.h>



			.arm



			.globl	at91sam9g45_restart



at91sam9g45_restart:

			ldr	r0, .at91_va_base_sdramc0	@ preload constants

			ldr	r1, =at91_rstc_base

			ldr	r1, [r1]



			mov	r2, #1

			mov	r3, #AT91_DDRSDRC_LPCB_POWER_DOWN

			ldr	r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST



			.balign	32				@ align to cache line



			str	r2, [r0, #AT91_DDRSDRC_RTR]	@ disable DDR0 access

			str	r3, [r0, #AT91_DDRSDRC_LPR]	@ power down DDR0

			str	r4, [r1, #AT91_RSTC_CR]		@ reset processor



			b	.



.at91_va_base_sdramc0:

	.word AT91_VA_BASE_SYS + AT91_DDRSDRC0