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Commit e9f68b5c authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Nicolas Ferre
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ARM: at91: make rstc soc independent

parent c0177594
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+1 −0
Original line number Diff line number Diff line
@@ -331,6 +331,7 @@ static void __init at91cap9_map_io(void)
static void __init at91cap9_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
	at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
	at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
}
+1 −0
Original line number Diff line number Diff line
@@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void)
static void __init at91sam9260_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
	at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
}
+1 −0
Original line number Diff line number Diff line
@@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void)
static void __init at91sam9261_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
	at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
}
+1 −0
Original line number Diff line number Diff line
@@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void)
static void __init at91sam9263_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
	at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
	at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
+3 −4
Original line number Diff line number Diff line
@@ -23,7 +23,8 @@
			.globl	at91sam9_alt_restart

at91sam9_alt_restart:	ldr	r0, .at91_va_base_sdramc	@ preload constants
			ldr	r1, .at91_va_base_rstc_cr
			ldr	r1, =at91_rstc_base
			ldr	r1, [r1]

			mov	r2, #1
			mov	r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants

			str	r2, [r0, #AT91_SDRAMC_TR]	@ disable SDRAM access
			str	r3, [r0, #AT91_SDRAMC_LPR]	@ power down SDRAM
			str	r4, [r1]			@ reset processor
			str	r4, [r1, #AT91_RSTC_CR]		@ reset processor

			b	.

.at91_va_base_sdramc:
	.word AT91_VA_BASE_SYS + AT91_SDRAMC0
.at91_va_base_rstc_cr:
	.word AT91_VA_BASE_SYS + AT91_RSTC_CR
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