Loading drivers/media/platform/msm/vidc/hfi_packetization.c +8 −0 Original line number Diff line number Diff line Loading @@ -1811,6 +1811,14 @@ int create_pkt_cmd_session_set_property( pkt->size += sizeof(u32) + sizeof(struct hfi_enable); break; } case HAL_CONFIG_VENC_PERF_MODE: { pkt->rg_property_data[0] = HFI_PROPERTY_CONFIG_VENC_PERF_MODE; pkt->rg_property_data[1] = *(u32 *)pdata; pkt->size += sizeof(u32) * 2; break; } /* FOLLOWING PROPERTIES ARE NOT IMPLEMENTED IN CORE YET */ case HAL_CONFIG_BUFFER_REQUIREMENTS: case HAL_CONFIG_PRIORITY: Loading drivers/media/platform/msm/vidc/msm_venc.c +16 −0 Original line number Diff line number Diff line Loading @@ -1033,6 +1033,16 @@ static struct msm_vidc_ctrl msm_venc_ctrls[] = { .default_value = V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_DISABLED, .step = 1, }, { .id = V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE, .name = "Set Encoder performance mode", .type = V4L2_CTRL_TYPE_INTEGER, .minimum = V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY, .maximum = V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE, .default_value = V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY, .step = 1, .qmenu = NULL, }, }; #define NUM_CTRLS ARRAY_SIZE(msm_venc_ctrls) Loading Loading @@ -1784,6 +1794,7 @@ static int try_set_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) struct hal_ltr_use use_ltr; struct hal_ltr_mark mark_ltr; u32 hier_p_layers; struct hal_venc_perf_mode venc_mode; if (!inst || !inst->core || !inst->core->device) { dprintk(VIDC_ERR, "%s invalid parameters\n", __func__); Loading Loading @@ -2618,6 +2629,11 @@ static int try_set_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) enable.enable = ctrl->val; pdata = &enable; break; case V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE: property_id = HAL_CONFIG_VENC_PERF_MODE; venc_mode.mode = ctrl->val; pdata = &venc_mode; break; default: dprintk(VIDC_ERR, "Unsupported index: %x\n", ctrl->id); rc = -ENOTSUPP; Loading drivers/media/platform/msm/vidc/vidc_hfi_api.h +5 −0 Original line number Diff line number Diff line Loading @@ -210,6 +210,7 @@ enum hal_property { HAL_PARAM_VPE_COLOR_SPACE_CONVERSION, HAL_PARAM_VENC_VPX_ERROR_RESILIENCE_MODE, HAL_PARAM_VENC_H264_NAL_SVC_EXT, HAL_CONFIG_VENC_PERF_MODE, }; enum hal_domain { Loading Loading @@ -1028,6 +1029,10 @@ struct hal_ltr_mark { u32 mark_frame; }; struct hal_venc_perf_mode { u32 mode; }; struct hfi_scs_threshold { u32 threshold_value; }; Loading drivers/media/platform/msm/vidc/vidc_hfi_helper.h +6 −0 Original line number Diff line number Diff line Loading @@ -211,6 +211,9 @@ #define HFI_BUFFER_INTERNAL_PERSIST (HFI_COMMON_BASE + 0x4) #define HFI_BUFFER_INTERNAL_PERSIST_1 (HFI_COMMON_BASE + 0x5) #define HFI_VENC_PERFMODE_MAX_QUALITY 0x1 #define HFI_VENC_PERFMODE_POWER_SAVE 0x2 struct hfi_buffer_info { u32 buffer_addr; u32 extra_data_addr; Loading Loading @@ -381,6 +384,9 @@ struct hfi_buffer_info { (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00B) #define HFI_PROPERTY_CONFIG_VENC_LTRPERIOD \ (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00C) #define HFI_PROPERTY_CONFIG_VENC_PERF_MODE \ (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00E) #define HFI_PROPERTY_CONFIG_VPE_COMMON_START \ (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x8000) #define HFI_PROPERTY_CONFIG_VPE_DEINTERLACE \ Loading include/uapi/linux/v4l2-controls.h +10 −2 Original line number Diff line number Diff line Loading @@ -926,7 +926,7 @@ enum vl42_mpeg_vidc_video_vpx_error_resilience { }; #define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE \ (V4L2_CID_MPEG_MSM_VIDC_BASE + 64) (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) enum v4l2_mpeg_video_hevc_profile { V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN = 0, V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN10 = 1, Loading @@ -934,7 +934,7 @@ enum v4l2_mpeg_video_hevc_profile { }; #define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL \ (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) (V4L2_CID_MPEG_MSM_VIDC_BASE + 66) enum v4l2_mpeg_video_hevc_level { V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_1 = 0, V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_1 = 1, Loading Loading @@ -972,6 +972,14 @@ enum vl42_mpeg_vidc_video_h264_svc_nal { V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_ENABLED = 1, }; #define V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE \ (V4L2_CID_MPEG_MSM_VIDC_BASE + 68) enum v4l2_mpeg_vidc_video_perf_mode { V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY = 1, V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE = 2 }; /* Camera class control IDs */ #define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) Loading Loading
drivers/media/platform/msm/vidc/hfi_packetization.c +8 −0 Original line number Diff line number Diff line Loading @@ -1811,6 +1811,14 @@ int create_pkt_cmd_session_set_property( pkt->size += sizeof(u32) + sizeof(struct hfi_enable); break; } case HAL_CONFIG_VENC_PERF_MODE: { pkt->rg_property_data[0] = HFI_PROPERTY_CONFIG_VENC_PERF_MODE; pkt->rg_property_data[1] = *(u32 *)pdata; pkt->size += sizeof(u32) * 2; break; } /* FOLLOWING PROPERTIES ARE NOT IMPLEMENTED IN CORE YET */ case HAL_CONFIG_BUFFER_REQUIREMENTS: case HAL_CONFIG_PRIORITY: Loading
drivers/media/platform/msm/vidc/msm_venc.c +16 −0 Original line number Diff line number Diff line Loading @@ -1033,6 +1033,16 @@ static struct msm_vidc_ctrl msm_venc_ctrls[] = { .default_value = V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_DISABLED, .step = 1, }, { .id = V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE, .name = "Set Encoder performance mode", .type = V4L2_CTRL_TYPE_INTEGER, .minimum = V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY, .maximum = V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE, .default_value = V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY, .step = 1, .qmenu = NULL, }, }; #define NUM_CTRLS ARRAY_SIZE(msm_venc_ctrls) Loading Loading @@ -1784,6 +1794,7 @@ static int try_set_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) struct hal_ltr_use use_ltr; struct hal_ltr_mark mark_ltr; u32 hier_p_layers; struct hal_venc_perf_mode venc_mode; if (!inst || !inst->core || !inst->core->device) { dprintk(VIDC_ERR, "%s invalid parameters\n", __func__); Loading Loading @@ -2618,6 +2629,11 @@ static int try_set_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl) enable.enable = ctrl->val; pdata = &enable; break; case V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE: property_id = HAL_CONFIG_VENC_PERF_MODE; venc_mode.mode = ctrl->val; pdata = &venc_mode; break; default: dprintk(VIDC_ERR, "Unsupported index: %x\n", ctrl->id); rc = -ENOTSUPP; Loading
drivers/media/platform/msm/vidc/vidc_hfi_api.h +5 −0 Original line number Diff line number Diff line Loading @@ -210,6 +210,7 @@ enum hal_property { HAL_PARAM_VPE_COLOR_SPACE_CONVERSION, HAL_PARAM_VENC_VPX_ERROR_RESILIENCE_MODE, HAL_PARAM_VENC_H264_NAL_SVC_EXT, HAL_CONFIG_VENC_PERF_MODE, }; enum hal_domain { Loading Loading @@ -1028,6 +1029,10 @@ struct hal_ltr_mark { u32 mark_frame; }; struct hal_venc_perf_mode { u32 mode; }; struct hfi_scs_threshold { u32 threshold_value; }; Loading
drivers/media/platform/msm/vidc/vidc_hfi_helper.h +6 −0 Original line number Diff line number Diff line Loading @@ -211,6 +211,9 @@ #define HFI_BUFFER_INTERNAL_PERSIST (HFI_COMMON_BASE + 0x4) #define HFI_BUFFER_INTERNAL_PERSIST_1 (HFI_COMMON_BASE + 0x5) #define HFI_VENC_PERFMODE_MAX_QUALITY 0x1 #define HFI_VENC_PERFMODE_POWER_SAVE 0x2 struct hfi_buffer_info { u32 buffer_addr; u32 extra_data_addr; Loading Loading @@ -381,6 +384,9 @@ struct hfi_buffer_info { (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00B) #define HFI_PROPERTY_CONFIG_VENC_LTRPERIOD \ (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00C) #define HFI_PROPERTY_CONFIG_VENC_PERF_MODE \ (HFI_PROPERTY_CONFIG_VENC_COMMON_START + 0x00E) #define HFI_PROPERTY_CONFIG_VPE_COMMON_START \ (HFI_DOMAIN_BASE_VPE + HFI_ARCH_COMMON_OFFSET + 0x8000) #define HFI_PROPERTY_CONFIG_VPE_DEINTERLACE \ Loading
include/uapi/linux/v4l2-controls.h +10 −2 Original line number Diff line number Diff line Loading @@ -926,7 +926,7 @@ enum vl42_mpeg_vidc_video_vpx_error_resilience { }; #define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE \ (V4L2_CID_MPEG_MSM_VIDC_BASE + 64) (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) enum v4l2_mpeg_video_hevc_profile { V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN = 0, V4L2_MPEG_VIDC_VIDEO_HEVC_PROFILE_MAIN10 = 1, Loading @@ -934,7 +934,7 @@ enum v4l2_mpeg_video_hevc_profile { }; #define V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL \ (V4L2_CID_MPEG_MSM_VIDC_BASE + 65) (V4L2_CID_MPEG_MSM_VIDC_BASE + 66) enum v4l2_mpeg_video_hevc_level { V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_MAIN_TIER_LEVEL_1 = 0, V4L2_MPEG_VIDC_VIDEO_HEVC_LEVEL_HIGH_TIER_LEVEL_1 = 1, Loading Loading @@ -972,6 +972,14 @@ enum vl42_mpeg_vidc_video_h264_svc_nal { V4L2_CID_MPEG_VIDC_VIDEO_H264_NAL_SVC_ENABLED = 1, }; #define V4L2_CID_MPEG_VIDC_VIDEO_PERF_MODE \ (V4L2_CID_MPEG_MSM_VIDC_BASE + 68) enum v4l2_mpeg_vidc_video_perf_mode { V4L2_MPEG_VIDC_VIDEO_PERF_MAX_QUALITY = 1, V4L2_MPEG_VIDC_VIDEO_PERF_POWER_SAVE = 2 }; /* Camera class control IDs */ #define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) Loading