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Commit 12665c1c authored by Vikram Mulukutla's avatar Vikram Mulukutla
Browse files

clk: qcom: clock-pll: Rework test control programming 



Variable rate PLLs may require an initial value to be
programmed into the test control registers, or require
test control programming as part of the enable sequence.
Provide for both options.

Change-Id: Ie1d1b3859aa87d31416220dae62118c9c88d0693
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent 6830e0cf

drivers/clk/qcom/clock-pll.c

+12 −2
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
							(x)->config_ctl_reg)

#define PLL_TEST_CTL_LO_REG(x)	(*(x)->base + (unsigned long) \

							(x)->test_ctl_lo_reg)

#define PLL_TEST_CTL_HI_REG(x)	(*(x)->base + (unsigned long) \

							(x)->test_ctl_hi_reg)

static DEFINE_SPINLOCK(pll_reg_lock);



#define ENABLE_WAIT_MAX_LOOPS 200
@@ -241,6 +243,12 @@ static void __variable_rate_pll_init(struct clk *c) 


	writel_relaxed(pll->vals.alpha_val, PLL_ALPHA_REG(pll));

	writel_relaxed(pll->vals.config_ctl_val, PLL_CFG_CTL_REG(pll));

	if (pll->init_test_ctl) {

		writel_relaxed(pll->vals.test_ctl_lo_val,

				PLL_TEST_CTL_LO_REG(pll));

		writel_relaxed(pll->vals.test_ctl_hi_val,

				PLL_TEST_CTL_HI_REG(pll));

	}



	pll->inited = true;

}
@@ -261,7 +269,8 @@ static int variable_rate_pll_clk_enable(struct clk *c) 
	mode = readl_relaxed(PLL_MODE_REG(pll));



	/* Set test control bits as required by HW doc */

	if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val)

	if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&

		pll->pgm_test_ctl_enable)

		writel_relaxed(pll->vals.test_ctl_lo_val,

				PLL_TEST_CTL_LO_REG(pll));
@@ -285,7 +294,8 @@ static int variable_rate_pll_clk_enable(struct clk *c) 
	udelay(10);



	/* Clear test control bits */

	if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val)

	if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&

		pll->pgm_test_ctl_enable)

		writel_relaxed(0x0, PLL_TEST_CTL_LO_REG(pll));



	/* Wait for pll to lock. */

include/soc/qcom/clock-pll.h

+7 −0
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ struct pll_config_vals { 
	u32 pre_div_masked;

	u32 config_ctl_val;

	u32 test_ctl_lo_val;

	u32 test_ctl_hi_val;

	u32 alpha_val;

	bool enable_mn;

};
@@ -115,6 +116,8 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *c) 
 *   post divider and vco configuration. register name can be configure register

 *   or user_ctl register depending on targets

 * @status_reg: status register, contains the lock detection bit

 * @init_test_ctl: initialize the test control register

 * @pgm_test_ctl_enable: program the test_ctl register in the enable sequence

 * @masks: masks used for settings in config_reg

 * @vals: configuration values to be written to PLL registers

 * @freq_tbl: pll freq table
@@ -131,6 +134,10 @@ struct pll_clk { 
	void __iomem *const config_ctl_reg;

	void __iomem *const status_reg;

	void __iomem *const test_ctl_lo_reg;

	void __iomem *const test_ctl_hi_reg;



	bool init_test_ctl;

	bool pgm_test_ctl_enable;



	struct pll_config_masks masks;

	struct pll_config_vals vals;