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Commit 0a61988e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: pcie: support L1ss for both RC0 and RC1"

parents 5b8b82de d177fb66

arch/arm/mach-msm/pcie.c

+7 −2
Original line number Diff line number Diff line
@@ -670,6 +670,11 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev) 


static void msm_pcie_config_l1ss(struct msm_pcie_dev_t *dev)

{

	u32 offset = 0;



	if (!dev->rc_idx)

		offset = PCIE20_EP_L1SUB_CTL1_OFFSET;



	/* Enable the AUX Clock and the Core Clk to be synchronous for L1SS*/

	if (!dev->aux_clk_sync)

		msm_pcie_write_mask(dev->parf +
@@ -693,7 +698,7 @@ static void msm_pcie_config_l1ss(struct msm_pcie_dev_t *dev) 
	msm_pcie_write_mask(dev->conf + PCIE20_CAP_LINKCTRLSTATUS, 0,

					BIT(1)|BIT(0));

	msm_pcie_write_mask(dev->conf + PCIE20_L1SUB_CONTROL1 +

					PCIE20_EP_L1SUB_CTL1_OFFSET, 0,

					offset, 0,

					BIT(3)|BIT(2)|BIT(1)|BIT(0));

	msm_pcie_write_mask(dev->conf + PCIE20_DEVICE_CONTROL2_STATUS2, 0,

					BIT(10));
@@ -701,7 +706,7 @@ static void msm_pcie_config_l1ss(struct msm_pcie_dev_t *dev) 
		readl_relaxed(dev->conf + PCIE20_CAP_LINKCTRLSTATUS));

	PCIE_DBG("EP's L1SUB_CONTROL1:0x%x\n",

		readl_relaxed(dev->conf + PCIE20_L1SUB_CONTROL1 +

					PCIE20_EP_L1SUB_CTL1_OFFSET));

					offset));

	PCIE_DBG("EP's DEVICE_CONTROL2_STATUS2:0x%x\n",

		readl_relaxed(dev->conf + PCIE20_DEVICE_CONTROL2_STATUS2));

}