Loading arch/arm/boot/dts/qcom/fsm9010-pinctrl.dtsi +11 −0 Original line number Diff line number Diff line Loading @@ -32,6 +32,17 @@ }; }; blsp1_uart3_active { qcom,pins = <&gp 10>, <&gp 11>; qcom,num-grp-pins = <2>; qcom,pin-func = <1>; label = "blsp1_uart3_active"; hsuart3_active: hsuart3_active { drive-strength = <8>; /* 8MA */ bias-disable; /* No PULL */ }; }; pcie0_clkreq { qcom,pins = <&gp 88>; qcom,num-grp-pins = <1>; Loading arch/arm/boot/dts/qcom/fsm9010.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,8 @@ clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; pinctrl-names = "default"; pinctrl-0 = <&hsuart3_active>; status = "disabled"; interrupts = <0 96 0>; }; Loading Loading
arch/arm/boot/dts/qcom/fsm9010-pinctrl.dtsi +11 −0 Original line number Diff line number Diff line Loading @@ -32,6 +32,17 @@ }; }; blsp1_uart3_active { qcom,pins = <&gp 10>, <&gp 11>; qcom,num-grp-pins = <2>; qcom,pin-func = <1>; label = "blsp1_uart3_active"; hsuart3_active: hsuart3_active { drive-strength = <8>; /* 8MA */ bias-disable; /* No PULL */ }; }; pcie0_clkreq { qcom,pins = <&gp 88>; qcom,num-grp-pins = <1>; Loading
arch/arm/boot/dts/qcom/fsm9010.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,8 @@ clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; pinctrl-names = "default"; pinctrl-0 = <&hsuart3_active>; status = "disabled"; interrupts = <0 96 0>; }; Loading