Loading arch/arm/boot/dts/qcom/fsm9010-rumi.dts +1 −2 Original line number Diff line number Diff line Loading @@ -21,8 +21,7 @@ }; &soc { serial@f991f000 { qcom,bus-speed-mode = ""; blsp1_uart2: serial@f991f000 { status = "ok"; }; Loading arch/arm/boot/dts/qcom/fsm9010-v1.0-cdp.dts +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ }; &soc { serial@f991f000 { blsp1_uart3: serial@f9920000 { status = "ok"; }; Loading arch/arm/boot/dts/qcom/fsm9010-v1.0-mtp.dts +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ &soc { serial@f991f000 { blsp1_uart3: serial@f9920000 { status = "ok"; }; Loading arch/arm/boot/dts/qcom/fsm9010.dtsi +11 −1 Original line number Diff line number Diff line Loading @@ -63,7 +63,7 @@ #clock-cells = <1>; }; serial@f991f000 { blsp1_uart2: serial@f991f000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf991f000 0x1000>; clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, Loading @@ -73,6 +73,16 @@ interrupts = <0 95 0>; }; blsp1_uart3: serial@f9920000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf9920000 0x1000>; clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; status = "disabled"; interrupts = <0 96 0>; }; qcom,smem@fa00000 { compatible = "qcom,smem"; reg = <0x0fa00000 0x200000>, Loading Loading
arch/arm/boot/dts/qcom/fsm9010-rumi.dts +1 −2 Original line number Diff line number Diff line Loading @@ -21,8 +21,7 @@ }; &soc { serial@f991f000 { qcom,bus-speed-mode = ""; blsp1_uart2: serial@f991f000 { status = "ok"; }; Loading
arch/arm/boot/dts/qcom/fsm9010-v1.0-cdp.dts +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ }; &soc { serial@f991f000 { blsp1_uart3: serial@f9920000 { status = "ok"; }; Loading
arch/arm/boot/dts/qcom/fsm9010-v1.0-mtp.dts +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ &soc { serial@f991f000 { blsp1_uart3: serial@f9920000 { status = "ok"; }; Loading
arch/arm/boot/dts/qcom/fsm9010.dtsi +11 −1 Original line number Diff line number Diff line Loading @@ -63,7 +63,7 @@ #clock-cells = <1>; }; serial@f991f000 { blsp1_uart2: serial@f991f000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf991f000 0x1000>; clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, Loading @@ -73,6 +73,16 @@ interrupts = <0 95 0>; }; blsp1_uart3: serial@f9920000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf9920000 0x1000>; clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; status = "disabled"; interrupts = <0 96 0>; }; qcom,smem@fa00000 { compatible = "qcom,smem"; reg = <0x0fa00000 0x200000>, Loading