Loading arch/arm/mach-davinci/da850.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -1055,7 +1055,7 @@ int da850_register_pm(struct platform_device *pdev) if (!pdata->cpupll_reg_base) if (!pdata->cpupll_reg_base) return -ENOMEM; return -ENOMEM; pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K); pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); if (!pdata->ddrpll_reg_base) { if (!pdata->ddrpll_reg_base) { ret = -ENOMEM; ret = -ENOMEM; goto no_ddrpll_mem; goto no_ddrpll_mem; Loading arch/arm/mach-davinci/devices-da8xx.c +9 −7 Original line number Original line Diff line number Diff line Loading @@ -24,23 +24,25 @@ #include "clock.h" #include "clock.h" #define DA8XX_TPCC_BASE 0x01c00000 #define DA8XX_TPCC_BASE 0x01c00000 #define DA850_MMCSD1_BASE 0x01e1b000 #define DA850_TPCC1_BASE 0x01e30000 #define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC1_BASE 0x01c08400 #define DA8XX_TPTC1_BASE 0x01c08400 #define DA850_TPTC2_BASE 0x01e38000 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ #define DA8XX_I2C0_BASE 0x01c22000 #define DA8XX_I2C0_BASE 0x01c22000 #define DA8XX_RTC_BASE 0x01C23000 #define DA8XX_RTC_BASE 0x01c23000 #define DA8XX_MMCSD0_BASE 0x01c40000 #define DA8XX_SPI0_BASE 0x01c41000 #define DA830_SPI1_BASE 0x01e12000 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 #define DA850_MMCSD1_BASE 0x01e1b000 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_I2C1_BASE 0x01e28000 #define DA8XX_I2C1_BASE 0x01e28000 #define DA8XX_SPI0_BASE 0x01c41000 #define DA850_TPCC1_BASE 0x01e30000 #define DA830_SPI1_BASE 0x01e12000 #define DA850_TPTC2_BASE 0x01e38000 #define DA850_SPI1_BASE 0x01f0e000 #define DA850_SPI1_BASE 0x01f0e000 #define DA8XX_DDR2_CTL_BASE 0xb0000000 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 Loading arch/arm/mach-davinci/devices.c +3 −0 Original line number Original line Diff line number Diff line Loading @@ -33,6 +33,9 @@ #define DM365_MMCSD0_BASE 0x01D11000 #define DM365_MMCSD0_BASE 0x01D11000 #define DM365_MMCSD1_BASE 0x01D00000 #define DM365_MMCSD1_BASE 0x01D00000 /* System control register offsets */ #define DM64XX_VDD3P3V_PWDN 0x48 static struct resource i2c_resources[] = { static struct resource i2c_resources[] = { { { .start = DAVINCI_I2C_BASE, .start = DAVINCI_I2C_BASE, Loading arch/arm/mach-davinci/include/mach/da8xx.h +0 −4 Original line number Original line Diff line number Diff line Loading @@ -64,13 +64,9 @@ extern unsigned int da850_max_speed; #define DA8XX_TIMER64P1_BASE 0x01c21000 #define DA8XX_TIMER64P1_BASE 0x01c21000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 #define DA8XX_PLL1_BASE 0x01e1a000 #define DA8XX_MMCSD0_BASE 0x01c40000 #define DA8XX_AEMIF_CS2_BASE 0x60000000 #define DA8XX_AEMIF_CS2_BASE 0x60000000 #define DA8XX_AEMIF_CS3_BASE 0x62000000 #define DA8XX_AEMIF_CS3_BASE 0x62000000 #define DA8XX_AEMIF_CTL_BASE 0x68000000 #define DA8XX_AEMIF_CTL_BASE 0x68000000 #define DA8XX_DDR2_CTL_BASE 0xb0000000 #define DA8XX_ARM_RAM_BASE 0xffff0000 #define DA8XX_ARM_RAM_BASE 0xffff0000 void __init da830_init(void); void __init da830_init(void); Loading arch/arm/mach-davinci/include/mach/hardware.h +0 −3 Original line number Original line Diff line number Diff line Loading @@ -21,9 +21,6 @@ */ */ #define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000 #define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000 /* System control register offsets */ #define DM64XX_VDD3P3V_PWDN 0x48 /* /* * I/O mapping * I/O mapping */ */ Loading Loading
arch/arm/mach-davinci/da850.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -1055,7 +1055,7 @@ int da850_register_pm(struct platform_device *pdev) if (!pdata->cpupll_reg_base) if (!pdata->cpupll_reg_base) return -ENOMEM; return -ENOMEM; pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K); pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); if (!pdata->ddrpll_reg_base) { if (!pdata->ddrpll_reg_base) { ret = -ENOMEM; ret = -ENOMEM; goto no_ddrpll_mem; goto no_ddrpll_mem; Loading
arch/arm/mach-davinci/devices-da8xx.c +9 −7 Original line number Original line Diff line number Diff line Loading @@ -24,23 +24,25 @@ #include "clock.h" #include "clock.h" #define DA8XX_TPCC_BASE 0x01c00000 #define DA8XX_TPCC_BASE 0x01c00000 #define DA850_MMCSD1_BASE 0x01e1b000 #define DA850_TPCC1_BASE 0x01e30000 #define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC1_BASE 0x01c08400 #define DA8XX_TPTC1_BASE 0x01c08400 #define DA850_TPTC2_BASE 0x01e38000 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ #define DA8XX_I2C0_BASE 0x01c22000 #define DA8XX_I2C0_BASE 0x01c22000 #define DA8XX_RTC_BASE 0x01C23000 #define DA8XX_RTC_BASE 0x01c23000 #define DA8XX_MMCSD0_BASE 0x01c40000 #define DA8XX_SPI0_BASE 0x01c41000 #define DA830_SPI1_BASE 0x01e12000 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 #define DA850_MMCSD1_BASE 0x01e1b000 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 #define DA8XX_EMAC_MDIO_BASE 0x01e24000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_I2C1_BASE 0x01e28000 #define DA8XX_I2C1_BASE 0x01e28000 #define DA8XX_SPI0_BASE 0x01c41000 #define DA850_TPCC1_BASE 0x01e30000 #define DA830_SPI1_BASE 0x01e12000 #define DA850_TPTC2_BASE 0x01e38000 #define DA850_SPI1_BASE 0x01f0e000 #define DA850_SPI1_BASE 0x01f0e000 #define DA8XX_DDR2_CTL_BASE 0xb0000000 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 Loading
arch/arm/mach-davinci/devices.c +3 −0 Original line number Original line Diff line number Diff line Loading @@ -33,6 +33,9 @@ #define DM365_MMCSD0_BASE 0x01D11000 #define DM365_MMCSD0_BASE 0x01D11000 #define DM365_MMCSD1_BASE 0x01D00000 #define DM365_MMCSD1_BASE 0x01D00000 /* System control register offsets */ #define DM64XX_VDD3P3V_PWDN 0x48 static struct resource i2c_resources[] = { static struct resource i2c_resources[] = { { { .start = DAVINCI_I2C_BASE, .start = DAVINCI_I2C_BASE, Loading
arch/arm/mach-davinci/include/mach/da8xx.h +0 −4 Original line number Original line Diff line number Diff line Loading @@ -64,13 +64,9 @@ extern unsigned int da850_max_speed; #define DA8XX_TIMER64P1_BASE 0x01c21000 #define DA8XX_TIMER64P1_BASE 0x01c21000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_GPIO_BASE 0x01e26000 #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_PSC1_BASE 0x01e27000 #define DA8XX_LCD_CNTRL_BASE 0x01e13000 #define DA8XX_PLL1_BASE 0x01e1a000 #define DA8XX_MMCSD0_BASE 0x01c40000 #define DA8XX_AEMIF_CS2_BASE 0x60000000 #define DA8XX_AEMIF_CS2_BASE 0x60000000 #define DA8XX_AEMIF_CS3_BASE 0x62000000 #define DA8XX_AEMIF_CS3_BASE 0x62000000 #define DA8XX_AEMIF_CTL_BASE 0x68000000 #define DA8XX_AEMIF_CTL_BASE 0x68000000 #define DA8XX_DDR2_CTL_BASE 0xb0000000 #define DA8XX_ARM_RAM_BASE 0xffff0000 #define DA8XX_ARM_RAM_BASE 0xffff0000 void __init da830_init(void); void __init da830_init(void); Loading
arch/arm/mach-davinci/include/mach/hardware.h +0 −3 Original line number Original line Diff line number Diff line Loading @@ -21,9 +21,6 @@ */ */ #define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000 #define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000 /* System control register offsets */ #define DM64XX_VDD3P3V_PWDN 0x48 /* /* * I/O mapping * I/O mapping */ */ Loading