Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e9126418 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Netlogic: Enable access to more than 64GB 



The ELPA bit needs to be set in the PAGEGRAIN register to enable
access to >64GB physical address. Update reset.S to do this from
every hardware thread.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6866/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a3deecfa

arch/mips/netlogic/common/reset.S

+15 −0
Original line number Original line Diff line number Diff line
@@ -73,6 +73,18 @@ 
	mtcr	t1, t0

	mtcr	t1, t0

.endm

.endm





/*

 * Allow access to physical mem >64G by enabling ELPA in PAGEGRAIN

 * register. This is needed before going to C code since the SP can

 * in this region. Called from all HW threads.

 */

.macro xlp_early_mmu_init

	mfc0	t0, CP0_PAGEMASK, 1

	li	t1, (1 << 29)		/* ELPA bit */

	or	t0, t1

	mtc0	t0, CP0_PAGEMASK, 1

.endm



/*

/*

 * L1D cache has to be flushed before enabling threads in XLP.

 * L1D cache has to be flushed before enabling threads in XLP.

 * On XLP8xx/XLP3xx, we do a low level flush using processor control

 * On XLP8xx/XLP3xx, we do a low level flush using processor control
@@ -228,6 +240,8 @@ EXPORT(nlm_boot_siblings) 
#endif

#endif

	mtc0	t1, CP0_STATUS

	mtc0	t1, CP0_STATUS





	xlp_early_mmu_init



	/* mark CPU ready */

	/* mark CPU ready */

	li	t3, CKSEG1ADDR(RESET_DATA_PHYS)

	li	t3, CKSEG1ADDR(RESET_DATA_PHYS)

	ADDIU	t1, t3, BOOT_CPU_READY

	ADDIU	t1, t3, BOOT_CPU_READY
@@ -254,6 +268,7 @@ EXPORT(nlm_reset_entry_end) 
LEAF(nlm_init_boot_cpu)

LEAF(nlm_init_boot_cpu)

#ifdef CONFIG_CPU_XLP

#ifdef CONFIG_CPU_XLP

	xlp_config_lsu

	xlp_config_lsu

	xlp_early_mmu_init

#endif

#endif

	jr	ra

	jr	ra

	nop

	nop