Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a3deecfa authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Netlogic: Reduce size of reset code 



Update thread wakeup function to use scratch registers for saving SP and
RA. Move the register restore code needed for thread 0 to the calling
function. This reduces the size of code copied to the reset vector.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6910/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 2e240ddd

arch/mips/netlogic/common/reset.S

+8 −7
Original line number Diff line number Diff line
@@ -197,6 +197,9 @@ FEXPORT(nlm_reset_entry) 
EXPORT(nlm_boot_siblings)

	/* core L1D flush before enable threads */

	xlp_flush_l1_dcache

	/* save ra and sp, will be used later (only for boot cpu) */

	dmtc0	ra, $22, 6

	dmtc0	sp, $22, 7

	/* Enable hw threads by writing to MAP_THREADMODE of the core */

	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)

	lw	t1, BOOT_THREAD_MODE(t0)	/* t1 <- thread mode */
@@ -238,14 +241,12 @@ EXPORT(nlm_boot_siblings) 
	nop



	/*

	 * For the boot CPU, we have to restore registers and

	 * return

	 * For the boot CPU, we have to restore ra and sp and return, rest

	 * of the registers will be restored by the caller

	 */

4:	dmfc0	t0, $4, 2	/* restore SP from UserLocal */

	li	t1, 0xfadebeef

	dmtc0	t1, $4, 2	/* restore SP from UserLocal */

	PTR_SUBU sp, t0, PT_SIZE

	RESTORE_ALL

4:

	dmfc0	ra, $22, 6

	dmfc0	sp, $22, 7

	jr	ra

	nop

EXPORT(nlm_reset_entry_end)

arch/mips/netlogic/common/smpboot.S

+8 −4
Original line number Diff line number Diff line
@@ -54,8 +54,9 @@ 
	.set	noat

	.set	arch=xlr		/* for mfcr/mtcr, XLR is sufficient */



FEXPORT(xlp_boot_core0_siblings)	/* "Master" cpu starts from here */

	dmtc0	sp, $4, 2		/* SP saved in UserLocal */

/* Called by the boot cpu to wake up its sibling threads */

NESTED(xlp_boot_core0_siblings, PT_SIZE, sp)

	/* CPU register contents lost when enabling threads, save them first */

	SAVE_ALL

	sync

	/* find the location to which nlm_boot_siblings was relocated */
@@ -65,9 +66,12 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ 
	dsubu	t2, t1

	daddu	t2, t0

	/* call it */

	jr	t2

	jalr	t2

	nop

	/* not reached */

	RESTORE_ALL

	jr	ra

	nop

END(xlp_boot_core0_siblings)



NESTED(nlm_boot_secondary_cpus, 16, sp)

	/* Initialize CP0 Status */