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Commit c9f3f2d8 authored by Masanari Iida's avatar Masanari Iida Committed by Jiri Kosina
Browse files

doc: Fix typo in doucmentations



Correct typo (double words) in documentations.

Signed-off-by: default avatarMasanari Iida <standby24x7@gmail.com>
Acked-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: default avatarJiri Kosina <jkosina@suse.cz>
parent 30abda17
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+1 −1
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@@ -78,7 +78,7 @@ to NULL. Drivers should use the following idiom:
The most common usage of these functions will probably be to specify
the maximum time from when an interrupt occurs, to when the device
becomes accessible.  To accomplish this, driver writers should use the
set_max_mpu_wakeup_lat() function to to constrain the MPU wakeup
set_max_mpu_wakeup_lat() function to constrain the MPU wakeup
latency, and the set_max_dev_wakeup_lat() function to constrain the
device wakeup latency (from clk_enable() to accessibility).  For
example,
+1 −1
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@@ -69,7 +69,7 @@ one, this value should be decreased relative to fifo_expire_async.
group_idle
-----------
This parameter forces idling at the CFQ group level instead of CFQ
queue level. This was introduced after after a bottleneck was observed
queue level. This was introduced after a bottleneck was observed
in higher end storage due to idle on sequential queue and allow dispatch
from a single queue. The idea with this parameter is that it can be run with
slice_idle=0 and group_idle=8, so that idling does not happen on individual
+2 −2
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@@ -32,8 +32,8 @@ numbers - see motherboard's TRM for more details.
The node describing a config device must refer to the sysreg node via
"arm,vexpress,config-bridge" phandle (can be also defined in the node's
parent) and relies on the board topology properties - see main vexpress
node documentation for more details. It must must also define the
following property:
node documentation for more details. It must also define the following
property:
- arm,vexpress-sysreg,func : must contain two cells:
  - first cell defines function number (eg. 1 for clock generator,
    2 for voltage regulators etc.)
+1 −1
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@@ -37,7 +37,7 @@ Bank: 3 (A, B and C)
  0xffffffff 0x7fff3ccf  /* pioB */
  0xffffffff 0x007fffff  /* pioC */

For each peripheral/bank we will descibe in a u32 if a pin can can be
For each peripheral/bank we will descibe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)

Let's take the pioA on peripheral B
+1 −1
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@@ -321,7 +321,7 @@ Access to a dma_buf from the kernel context involves three steps:

   When the importer is done accessing the range specified in begin_cpu_access,
   it needs to announce this to the exporter (to facilitate cache flushing and
   unpinning of any pinned resources). The result of of any dma_buf kmap calls
   unpinning of any pinned resources). The result of any dma_buf kmap calls
   after end_cpu_access is undefined.

   Interface:
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