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Commit 30abda17 authored by Sachin Kamat's avatar Sachin Kamat Committed by Jiri Kosina
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Documentation: clk: Fix a trivial typo in audss 



Fixes a trivial typo.

Signed-off-by: default avatarSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: default avatarJiri Kosina <jkosina@suse.cz>
parent 9ca18397

Documentation/devicetree/bindings/clock/clk-exynos-audss.txt

+1 −1
Original line number Original line Diff line number Diff line
@@ -2,7 +2,7 @@ 




The Samsung Audio Subsystem clock controller generates and supplies clocks

The Samsung Audio Subsystem clock controller generates and supplies clocks

to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock

to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock

binding described here is applicable to all SoC's in Exynos family.

binding described here is applicable to all SoCs in Exynos family.





Required Properties:

Required Properties: