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Commit c1e46580 authored by Yan, Zheng's avatar Yan, Zheng Committed by Ingo Molnar
Browse files

perf/x86/uncore: move NHM-EX/WSM-EX specific code to seperate file 



Signed-off-by: default avatarYan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Borislav Petkov <bp@suse.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Stephane Eranian <eranian@google.com>
Link: http://lkml.kernel.org/r/1406704935-27708-4-git-send-email-zheng.z.yan@intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 8268fdfc

arch/x86/kernel/cpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ endif 
obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_p6.o perf_event_knc.o perf_event_p4.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_uncore.o perf_event_intel_uncore_snb.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_uncore_snbep.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_uncore_snbep.o perf_event_intel_uncore_nhmex.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_rapl.o

endif

arch/x86/kernel/cpu/perf_event_intel_uncore.c

+2 −1036

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arch/x86/kernel/cpu/perf_event_intel_uncore.h

+3 −182
Original line number Diff line number Diff line
@@ -24,188 +24,6 @@ 


#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)



/* NHM-EX event control */

#define NHMEX_PMON_CTL_EV_SEL_MASK	0x000000ff

#define NHMEX_PMON_CTL_UMASK_MASK	0x0000ff00

#define NHMEX_PMON_CTL_EN_BIT0		(1 << 0)

#define NHMEX_PMON_CTL_EDGE_DET		(1 << 18)

#define NHMEX_PMON_CTL_PMI_EN		(1 << 20)

#define NHMEX_PMON_CTL_EN_BIT22		(1 << 22)

#define NHMEX_PMON_CTL_INVERT		(1 << 23)

#define NHMEX_PMON_CTL_TRESH_MASK	0xff000000

#define NHMEX_PMON_RAW_EVENT_MASK	(NHMEX_PMON_CTL_EV_SEL_MASK | \

					 NHMEX_PMON_CTL_UMASK_MASK | \

					 NHMEX_PMON_CTL_EDGE_DET | \

					 NHMEX_PMON_CTL_INVERT | \

					 NHMEX_PMON_CTL_TRESH_MASK)



/* NHM-EX Ubox */

#define NHMEX_U_MSR_PMON_GLOBAL_CTL		0xc00

#define NHMEX_U_MSR_PMON_CTR			0xc11

#define NHMEX_U_MSR_PMON_EV_SEL			0xc10



#define NHMEX_U_PMON_GLOBAL_EN			(1 << 0)

#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL	0x0000001e

#define NHMEX_U_PMON_GLOBAL_EN_ALL		(1 << 28)

#define NHMEX_U_PMON_GLOBAL_RST_ALL		(1 << 29)

#define NHMEX_U_PMON_GLOBAL_FRZ_ALL		(1 << 31)



#define NHMEX_U_PMON_RAW_EVENT_MASK		\

		(NHMEX_PMON_CTL_EV_SEL_MASK |	\

		 NHMEX_PMON_CTL_EDGE_DET)



/* NHM-EX Cbox */

#define NHMEX_C0_MSR_PMON_GLOBAL_CTL		0xd00

#define NHMEX_C0_MSR_PMON_CTR0			0xd11

#define NHMEX_C0_MSR_PMON_EV_SEL0		0xd10

#define NHMEX_C_MSR_OFFSET			0x20



/* NHM-EX Bbox */

#define NHMEX_B0_MSR_PMON_GLOBAL_CTL		0xc20

#define NHMEX_B0_MSR_PMON_CTR0			0xc31

#define NHMEX_B0_MSR_PMON_CTL0			0xc30

#define NHMEX_B_MSR_OFFSET			0x40

#define NHMEX_B0_MSR_MATCH			0xe45

#define NHMEX_B0_MSR_MASK			0xe46

#define NHMEX_B1_MSR_MATCH			0xe4d

#define NHMEX_B1_MSR_MASK			0xe4e



#define NHMEX_B_PMON_CTL_EN			(1 << 0)

#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT		1

#define NHMEX_B_PMON_CTL_EV_SEL_MASK		\

		(0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)

#define NHMEX_B_PMON_CTR_SHIFT		6

#define NHMEX_B_PMON_CTR_MASK		\

		(0x3 << NHMEX_B_PMON_CTR_SHIFT)

#define NHMEX_B_PMON_RAW_EVENT_MASK		\

		(NHMEX_B_PMON_CTL_EV_SEL_MASK | \

		 NHMEX_B_PMON_CTR_MASK)



/* NHM-EX Sbox */

#define NHMEX_S0_MSR_PMON_GLOBAL_CTL		0xc40

#define NHMEX_S0_MSR_PMON_CTR0			0xc51

#define NHMEX_S0_MSR_PMON_CTL0			0xc50

#define NHMEX_S_MSR_OFFSET			0x80

#define NHMEX_S0_MSR_MM_CFG			0xe48

#define NHMEX_S0_MSR_MATCH			0xe49

#define NHMEX_S0_MSR_MASK			0xe4a

#define NHMEX_S1_MSR_MM_CFG			0xe58

#define NHMEX_S1_MSR_MATCH			0xe59

#define NHMEX_S1_MSR_MASK			0xe5a



#define NHMEX_S_PMON_MM_CFG_EN			(0x1ULL << 63)

#define NHMEX_S_EVENT_TO_R_PROG_EV		0



/* NHM-EX Mbox */

#define NHMEX_M0_MSR_GLOBAL_CTL			0xca0

#define NHMEX_M0_MSR_PMU_DSP			0xca5

#define NHMEX_M0_MSR_PMU_ISS			0xca6

#define NHMEX_M0_MSR_PMU_MAP			0xca7

#define NHMEX_M0_MSR_PMU_MSC_THR		0xca8

#define NHMEX_M0_MSR_PMU_PGT			0xca9

#define NHMEX_M0_MSR_PMU_PLD			0xcaa

#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC		0xcab

#define NHMEX_M0_MSR_PMU_CTL0			0xcb0

#define NHMEX_M0_MSR_PMU_CNT0			0xcb1

#define NHMEX_M_MSR_OFFSET			0x40

#define NHMEX_M0_MSR_PMU_MM_CFG			0xe54

#define NHMEX_M1_MSR_PMU_MM_CFG			0xe5c



#define NHMEX_M_PMON_MM_CFG_EN			(1ULL << 63)

#define NHMEX_M_PMON_ADDR_MATCH_MASK		0x3ffffffffULL

#define NHMEX_M_PMON_ADDR_MASK_MASK		0x7ffffffULL

#define NHMEX_M_PMON_ADDR_MASK_SHIFT		34



#define NHMEX_M_PMON_CTL_EN			(1 << 0)

#define NHMEX_M_PMON_CTL_PMI_EN			(1 << 1)

#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT	2

#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK	\

	(0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)

#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT	4

#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK	\

	(0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)

#define NHMEX_M_PMON_CTL_WRAP_MODE		(1 << 6)

#define NHMEX_M_PMON_CTL_FLAG_MODE		(1 << 7)

#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT		9

#define NHMEX_M_PMON_CTL_INC_SEL_MASK		\

	(0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)

#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT	19

#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK	\

	(0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)

#define NHMEX_M_PMON_RAW_EVENT_MASK			\

		(NHMEX_M_PMON_CTL_COUNT_MODE_MASK |	\

		 NHMEX_M_PMON_CTL_STORAGE_MODE_MASK |	\

		 NHMEX_M_PMON_CTL_WRAP_MODE |		\

		 NHMEX_M_PMON_CTL_FLAG_MODE |		\

		 NHMEX_M_PMON_CTL_INC_SEL_MASK |	\

		 NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)



#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK		(((1 << 11) - 1) | (1 << 23))

#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)	(0x7ULL << (11 + 3 * (n)))



#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK		(((1 << 12) - 1) | (1 << 24))

#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)	(0x7ULL << (12 + 3 * (n)))



/*

 * use the 9~13 bits to select event If the 7th bit is not set,

 * otherwise use the 19~21 bits to select event.

 */

#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)

#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \

				NHMEX_M_PMON_CTL_FLAG_MODE)

#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \

			   NHMEX_M_PMON_CTL_FLAG_MODE)

#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \

				NHMEX_M_PMON_CTL_FLAG_MODE)

#define MBOX_INC_SEL_EXTAR_REG(c, r) \

		EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \

				MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)

#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \

		EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \

				MBOX_SET_FLAG_SEL_MASK, \

				(u64)-1, NHMEX_M_##r)



/* NHM-EX Rbox */

#define NHMEX_R_MSR_GLOBAL_CTL			0xe00

#define NHMEX_R_MSR_PMON_CTL0			0xe10

#define NHMEX_R_MSR_PMON_CNT0			0xe11

#define NHMEX_R_MSR_OFFSET			0x20



#define NHMEX_R_MSR_PORTN_QLX_CFG(n)		\

		((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))

#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n)		(0xe04 + (n))

#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n)		(0xe24 + (n))

#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n)		\

		(((n) < 4 ? 0 : 0x10) + (n) * 4)

#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n)	\

		(0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))

#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)

#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)

#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n)	\

		(0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))

#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)

#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)



#define NHMEX_R_PMON_CTL_EN			(1 << 0)

#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT		1

#define NHMEX_R_PMON_CTL_EV_SEL_MASK		\

		(0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)

#define NHMEX_R_PMON_CTL_PMI_EN			(1 << 6)

#define NHMEX_R_PMON_RAW_EVENT_MASK		NHMEX_R_PMON_CTL_EV_SEL_MASK



/* NHM-EX Wbox */

#define NHMEX_W_MSR_GLOBAL_CTL			0xc80

#define NHMEX_W_MSR_PMON_CNT0			0xc90

#define NHMEX_W_MSR_PMON_EVT_SEL0		0xc91

#define NHMEX_W_MSR_PMON_FIXED_CTR		0x394

#define NHMEX_W_MSR_PMON_FIXED_CTL		0x395



#define NHMEX_W_PMON_GLOBAL_FIXED_EN		(1ULL << 31)



struct intel_uncore_ops;

struct intel_uncore_pmu;

struct intel_uncore_box;
@@ -514,3 +332,6 @@ int snbep_uncore_pci_init(void); 
void snbep_uncore_cpu_init(void);

int ivt_uncore_pci_init(void);

void ivt_uncore_cpu_init(void);



/* perf_event_intel_uncore_nhmex.c */

void nhmex_uncore_cpu_init(void);

arch/x86/kernel/cpu/perf_event_intel_uncore_nhmex.c

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