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Commit 8268fdfc authored by Yan, Zheng's avatar Yan, Zheng Committed by Ingo Molnar
Browse files

perf/x86/uncore: Move SNB/IVB-EP specific code to seperate file 



Signed-off-by: default avatarYan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Borislav Petkov <bp@suse.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Stephane Eranian <eranian@google.com>
Link: http://lkml.kernel.org/r/1406704935-27708-3-git-send-email-zheng.z.yan@intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 92807ffd

arch/x86/kernel/cpu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ endif 
obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_p6.o perf_event_knc.o perf_event_p4.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_uncore.o perf_event_intel_uncore_snb.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_uncore_snbep.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_rapl.o

endif

arch/x86/kernel/cpu/perf_event_intel_uncore.c

+4 −1461

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arch/x86/kernel/cpu/perf_event_intel_uncore.h

+6 −158
Original line number Diff line number Diff line
@@ -24,164 +24,6 @@ 


#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)



/* SNB-EP Box level control */

#define SNBEP_PMON_BOX_CTL_RST_CTRL	(1 << 0)

#define SNBEP_PMON_BOX_CTL_RST_CTRS	(1 << 1)

#define SNBEP_PMON_BOX_CTL_FRZ		(1 << 8)

#define SNBEP_PMON_BOX_CTL_FRZ_EN	(1 << 16)

#define SNBEP_PMON_BOX_CTL_INT		(SNBEP_PMON_BOX_CTL_RST_CTRL | \

					 SNBEP_PMON_BOX_CTL_RST_CTRS | \

					 SNBEP_PMON_BOX_CTL_FRZ_EN)

/* SNB-EP event control */

#define SNBEP_PMON_CTL_EV_SEL_MASK	0x000000ff

#define SNBEP_PMON_CTL_UMASK_MASK	0x0000ff00

#define SNBEP_PMON_CTL_RST		(1 << 17)

#define SNBEP_PMON_CTL_EDGE_DET		(1 << 18)

#define SNBEP_PMON_CTL_EV_SEL_EXT	(1 << 21)

#define SNBEP_PMON_CTL_EN		(1 << 22)

#define SNBEP_PMON_CTL_INVERT		(1 << 23)

#define SNBEP_PMON_CTL_TRESH_MASK	0xff000000

#define SNBEP_PMON_RAW_EVENT_MASK	(SNBEP_PMON_CTL_EV_SEL_MASK | \

					 SNBEP_PMON_CTL_UMASK_MASK | \

					 SNBEP_PMON_CTL_EDGE_DET | \

					 SNBEP_PMON_CTL_INVERT | \

					 SNBEP_PMON_CTL_TRESH_MASK)



/* SNB-EP Ubox event control */

#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK		0x1f000000

#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK		\

				(SNBEP_PMON_CTL_EV_SEL_MASK | \

				 SNBEP_PMON_CTL_UMASK_MASK | \

				 SNBEP_PMON_CTL_EDGE_DET | \

				 SNBEP_PMON_CTL_INVERT | \

				 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)



#define SNBEP_CBO_PMON_CTL_TID_EN		(1 << 19)

#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK	(SNBEP_PMON_RAW_EVENT_MASK | \

						 SNBEP_CBO_PMON_CTL_TID_EN)



/* SNB-EP PCU event control */

#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK	0x0000c000

#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK	0x1f000000

#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT	(1 << 30)

#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET	(1 << 31)

#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK	\

				(SNBEP_PMON_CTL_EV_SEL_MASK | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \

				 SNBEP_PMON_CTL_EDGE_DET | \

				 SNBEP_PMON_CTL_EV_SEL_EXT | \

				 SNBEP_PMON_CTL_INVERT | \

				 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)



#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK	\

				(SNBEP_PMON_RAW_EVENT_MASK | \

				 SNBEP_PMON_CTL_EV_SEL_EXT)



/* SNB-EP pci control register */

#define SNBEP_PCI_PMON_BOX_CTL			0xf4

#define SNBEP_PCI_PMON_CTL0			0xd8

/* SNB-EP pci counter register */

#define SNBEP_PCI_PMON_CTR0			0xa0



/* SNB-EP home agent register */

#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0	0x40

#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1	0x44

#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH	0x48

/* SNB-EP memory controller register */

#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL		0xf0

#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR		0xd0

/* SNB-EP QPI register */

#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0		0x228

#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1		0x22c

#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0		0x238

#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1		0x23c



/* SNB-EP Ubox register */

#define SNBEP_U_MSR_PMON_CTR0			0xc16

#define SNBEP_U_MSR_PMON_CTL0			0xc10



#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL		0xc08

#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR		0xc09



/* SNB-EP Cbo register */

#define SNBEP_C0_MSR_PMON_CTR0			0xd16

#define SNBEP_C0_MSR_PMON_CTL0			0xd10

#define SNBEP_C0_MSR_PMON_BOX_CTL		0xd04

#define SNBEP_C0_MSR_PMON_BOX_FILTER		0xd14

#define SNBEP_CBO_MSR_OFFSET			0x20



#define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID	0x1f

#define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID	0x3fc00

#define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE	0x7c0000

#define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC	0xff800000



#define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) {	\

	.event = (e),				\

	.msr = SNBEP_C0_MSR_PMON_BOX_FILTER,	\

	.config_mask = (m),			\

	.idx = (i)				\

}



/* SNB-EP PCU register */

#define SNBEP_PCU_MSR_PMON_CTR0			0xc36

#define SNBEP_PCU_MSR_PMON_CTL0			0xc30

#define SNBEP_PCU_MSR_PMON_BOX_CTL		0xc24

#define SNBEP_PCU_MSR_PMON_BOX_FILTER		0xc34

#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK	0xffffffff

#define SNBEP_PCU_MSR_CORE_C3_CTR		0x3fc

#define SNBEP_PCU_MSR_CORE_C6_CTR		0x3fd



/* IVT event control */

#define IVT_PMON_BOX_CTL_INT		(SNBEP_PMON_BOX_CTL_RST_CTRL | \

					 SNBEP_PMON_BOX_CTL_RST_CTRS)

#define IVT_PMON_RAW_EVENT_MASK		(SNBEP_PMON_CTL_EV_SEL_MASK | \

					 SNBEP_PMON_CTL_UMASK_MASK | \

					 SNBEP_PMON_CTL_EDGE_DET | \

					 SNBEP_PMON_CTL_TRESH_MASK)

/* IVT Ubox */

#define IVT_U_MSR_PMON_GLOBAL_CTL		0xc00

#define IVT_U_PMON_GLOBAL_FRZ_ALL		(1 << 31)

#define IVT_U_PMON_GLOBAL_UNFRZ_ALL		(1 << 29)



#define IVT_U_MSR_PMON_RAW_EVENT_MASK	\

				(SNBEP_PMON_CTL_EV_SEL_MASK | \

				 SNBEP_PMON_CTL_UMASK_MASK | \

				 SNBEP_PMON_CTL_EDGE_DET | \

				 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)

/* IVT Cbo */

#define IVT_CBO_MSR_PMON_RAW_EVENT_MASK		(IVT_PMON_RAW_EVENT_MASK | \

						 SNBEP_CBO_PMON_CTL_TID_EN)



#define IVT_CB0_MSR_PMON_BOX_FILTER_TID		(0x1fULL << 0)

#define IVT_CB0_MSR_PMON_BOX_FILTER_LINK	(0xfULL << 5)

#define IVT_CB0_MSR_PMON_BOX_FILTER_STATE	(0x3fULL << 17)

#define IVT_CB0_MSR_PMON_BOX_FILTER_NID		(0xffffULL << 32)

#define IVT_CB0_MSR_PMON_BOX_FILTER_OPC		(0x1ffULL << 52)

#define IVT_CB0_MSR_PMON_BOX_FILTER_C6		(0x1ULL << 61)

#define IVT_CB0_MSR_PMON_BOX_FILTER_NC		(0x1ULL << 62)

#define IVT_CB0_MSR_PMON_BOX_FILTER_IOSC	(0x1ULL << 63)



/* IVT home agent */

#define IVT_HA_PCI_PMON_CTL_Q_OCC_RST		(1 << 16)

#define IVT_HA_PCI_PMON_RAW_EVENT_MASK		\

				(IVT_PMON_RAW_EVENT_MASK | \

				 IVT_HA_PCI_PMON_CTL_Q_OCC_RST)

/* IVT PCU */

#define IVT_PCU_MSR_PMON_RAW_EVENT_MASK	\

				(SNBEP_PMON_CTL_EV_SEL_MASK | \

				 SNBEP_PMON_CTL_EV_SEL_EXT | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \

				 SNBEP_PMON_CTL_EDGE_DET | \

				 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)

/* IVT QPI */

#define IVT_QPI_PCI_PMON_RAW_EVENT_MASK	\

				(IVT_PMON_RAW_EVENT_MASK | \

				 SNBEP_PMON_CTL_EV_SEL_EXT)



/* NHM-EX event control */

#define NHMEX_PMON_CTL_EV_SEL_MASK	0x000000ff

#define NHMEX_PMON_CTL_UMASK_MASK	0x0000ff00
@@ -666,3 +508,9 @@ int ivb_uncore_pci_init(void); 
int hsw_uncore_pci_init(void);

void snb_uncore_cpu_init(void);

void nhm_uncore_cpu_init(void);



/* perf_event_intel_uncore_snbep.c */

int snbep_uncore_pci_init(void);

void snbep_uncore_cpu_init(void);

int ivt_uncore_pci_init(void);

void ivt_uncore_cpu_init(void);

arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c

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