DEVICETREE: Add bindings for the ATH79 MISC interrupt controllers

Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller

The MISC interrupt controller is a secondary controller for lower priority

interrupt.

Required Properties:

- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"

  as fallback

- reg: Base address and size of the controllers memory area

- interrupt-parent: phandle of the parent interrupt controller.

- interrupts: Interrupt specifier for the controllers interrupt.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode interrupt

		     source, should be 1

Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.

Example:

	interrupt-controller@18060010 {

		compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc";

		reg = <0x18060010 0x4>;

		interrupt-parent = <&cpuintc>;

		interrupts = <6>;

		interrupt-controller;

		#interrupt-cells = <1>;

	};