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Commit 1f5d76db authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: enable trickle feed on Haswell 



We shouldn't disable the trickle feed bits on Haswell. Our
documentation explicitly says the trickle feed bits of PRI_CTL and
CUR_CTL should not be programmed to 1, and the hardware engineer also
asked us to not program the SPR_CTL field to 1. Leaving the bits as 1
could cause underflows.

Reported-by: default avatarArthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 814c5f1f

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -3313,6 +3313,7 @@ 
#define   MCURSOR_PIPE_A	0x00

#define   MCURSOR_PIPE_A	0x00

#define   MCURSOR_PIPE_B	(1 << 28)

#define   MCURSOR_PIPE_B	(1 << 28)

#define   MCURSOR_GAMMA_ENABLE  (1 << 26)

#define   MCURSOR_GAMMA_ENABLE  (1 << 26)

#define   CURSOR_TRICKLE_FEED_DISABLE	(1 << 14)

#define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)

#define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)

#define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)

#define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)

#define   CURSOR_POS_MASK       0x007FF

#define   CURSOR_POS_MASK       0x007FF

drivers/gpu/drm/i915/intel_display.c

+7 −3
Original line number Original line Diff line number Diff line
@@ -2077,7 +2077,9 @@ static int ironlake_update_plane(struct drm_crtc *crtc, 
	else

	else

		dspcntr &= ~DISPPLANE_TILED;

		dspcntr &= ~DISPPLANE_TILED;





	/* must disable */

	if (IS_HASWELL(dev))

		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;

	else

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;





	I915_WRITE(reg, dspcntr);

	I915_WRITE(reg, dspcntr);
@@ -6762,8 +6764,10 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);

			cntl |= CURSOR_MODE_DISABLE;

			cntl |= CURSOR_MODE_DISABLE;

		}

		}

		if (IS_HASWELL(dev))

		if (IS_HASWELL(dev)) {

			cntl |= CURSOR_PIPE_CSC_ENABLE;

			cntl |= CURSOR_PIPE_CSC_ENABLE;

			cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;

		}

		I915_WRITE(CURCNTR_IVB(pipe), cntl);

		I915_WRITE(CURCNTR_IVB(pipe), cntl);





		intel_crtc->cursor_visible = visible;

		intel_crtc->cursor_visible = visible;

drivers/gpu/drm/i915/intel_pm.c

+0 −2
Original line number Original line Diff line number Diff line
@@ -4960,8 +4960,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);

			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);





	g4x_disable_trickle_feed(dev);



	/* WaVSRefCountFullforceMissDisable:hsw */

	/* WaVSRefCountFullforceMissDisable:hsw */

	gen7_setup_fixed_func_scheduler(dev_priv);

	gen7_setup_fixed_func_scheduler(dev_priv);

drivers/gpu/drm/i915/intel_sprite.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -260,8 +260,11 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	if (obj->tiling_mode != I915_TILING_NONE)

	if (obj->tiling_mode != I915_TILING_NONE)

		sprctl |= SPRITE_TILED;

		sprctl |= SPRITE_TILED;





	/* must disable */

	if (IS_HASWELL(dev))

		sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;

	else

		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;

		sprctl |= SPRITE_TRICKLE_FEED_DISABLE;



	sprctl |= SPRITE_ENABLE;

	sprctl |= SPRITE_ENABLE;





	if (IS_HASWELL(dev))

	if (IS_HASWELL(dev))