Loading arch/parisc/kernel/pci.c +5 −2 Original line number Original line Diff line number Diff line Loading @@ -18,7 +18,6 @@ #include <asm/io.h> #include <asm/io.h> #include <asm/system.h> #include <asm/system.h> #include <asm/cache.h> /* for L1_CACHE_BYTES */ #include <asm/superio.h> #include <asm/superio.h> #define DEBUG_RESOURCES 0 #define DEBUG_RESOURCES 0 Loading Loading @@ -123,6 +122,10 @@ static int __init pcibios_init(void) } else { } else { printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); } } /* Set the CLS for PCI as early as possible. */ pci_cache_line_size = pci_dfl_cache_line_size; return 0; return 0; } } Loading Loading @@ -171,7 +174,7 @@ void pcibios_set_master(struct pci_dev *dev) ** upper byte is PCI_LATENCY_TIMER. ** upper byte is PCI_LATENCY_TIMER. */ */ pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); (0x80 << 8) | pci_cache_line_size); } } Loading Loading
arch/parisc/kernel/pci.c +5 −2 Original line number Original line Diff line number Diff line Loading @@ -18,7 +18,6 @@ #include <asm/io.h> #include <asm/io.h> #include <asm/system.h> #include <asm/system.h> #include <asm/cache.h> /* for L1_CACHE_BYTES */ #include <asm/superio.h> #include <asm/superio.h> #define DEBUG_RESOURCES 0 #define DEBUG_RESOURCES 0 Loading Loading @@ -123,6 +122,10 @@ static int __init pcibios_init(void) } else { } else { printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); } } /* Set the CLS for PCI as early as possible. */ pci_cache_line_size = pci_dfl_cache_line_size; return 0; return 0; } } Loading Loading @@ -171,7 +174,7 @@ void pcibios_set_master(struct pci_dev *dev) ** upper byte is PCI_LATENCY_TIMER. ** upper byte is PCI_LATENCY_TIMER. */ */ pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); (0x80 << 8) | pci_cache_line_size); } } Loading