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Commit 5fd4514b authored by Carlos O'Donell's avatar Carlos O'Donell Committed by Kyle McMartin
Browse files

parisc: Set PCI CLS early in boot. 



Set the PCI CLS early in the boot process to prevent
device failures. In pcibios_set_master use the new
pci_cache_line_size instead of a hard-coded value.

Signed-off-by: default avatarCarlos O'Donell <carlos@codesourcery.com>
Reviewed-by: default avatarGrant Grundler <grundler@google.com>
Signed-off-by: default avatarKyle McMartin <kyle@redhat.com>
parent 75ef7cdd

arch/parisc/kernel/pci.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -18,7 +18,6 @@ 




#include <asm/io.h>

#include <asm/io.h>

#include <asm/system.h>

#include <asm/system.h>

#include <asm/cache.h>		/* for L1_CACHE_BYTES */

#include <asm/superio.h>

#include <asm/superio.h>





#define DEBUG_RESOURCES 0

#define DEBUG_RESOURCES 0
@@ -123,6 +122,10 @@ static int __init pcibios_init(void) 
	} else {

	} else {

		printk(KERN_WARNING "pci_bios != NULL but init() is!\n");

		printk(KERN_WARNING "pci_bios != NULL but init() is!\n");

	}

	}



	/* Set the CLS for PCI as early as possible. */

	pci_cache_line_size = pci_dfl_cache_line_size;



	return 0;

	return 0;

}

}
@@ -171,7 +174,7 @@ void pcibios_set_master(struct pci_dev *dev) 
	** upper byte is PCI_LATENCY_TIMER.

	** upper byte is PCI_LATENCY_TIMER.

	*/

	*/

	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,

	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,

				(0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));

			      (0x80 << 8) | pci_cache_line_size);

}

}