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Commit b990f9b3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 "Nothing controversial, just another batch of fixes:

   - Samsung/exynos fixes for more merge window fallout: build errors
     and warnings mostly, but also some clock/device setup issues on
     exynos4/5
   - PXA bug and warning fixes related to gpio and pinmux
   - IRQ domain conversion bugfixes for U300 and MSM
   - A regulator setup fix for U300"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: PXA2xx: MFP: fix potential direction bug
  ARM: PXA2xx: MFP: fix bug with MFP_LPM_KEEP_OUTPUT
  arm/sa1100: fix sa1100-rtc memory resource
  ARM: pxa: fix gpio wakeup setting
  ARM: SAMSUNG: add missing MMC_CAP2_BROKEN_VOLTAGE capability
  ARM: EXYNOS: Fix compilation error when CONFIG_OF is not defined
  ARM: EXYNOS: Fix resource on dev-dwmci.c
  ARM: S3C24XX: Fix build warning for S3C2410_PM
  ARM: mini2440_defconfig: Fix build error
  ARM: msm: Fix gic irqdomain support
  ARM: EXYNOS: Fix incorrect initialization of GIC
  ARM: EXYNOS: use 'exynos4-sdhci' as device name for sdhci controllers
  ARM: u300: bump all IRQ numbers by one
  ARM: ux300: Fix unimplementable regulation constraints
parents cd88e3a6 6e76538b

arch/arm/boot/dts/msm8660-surf.dts

+2 −2
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 
	intc: interrupt-controller@02080000 {

		compatible = "qcom,msm-8660-qgic";

		interrupt-controller;

		#interrupt-cells = <1>;

		#interrupt-cells = <3>;

		reg = < 0x02080000 0x1000 >,

		      < 0x02081000 0x1000 >;

	};
@@ -19,6 +19,6 @@ 
		compatible = "qcom,msm-hsuart", "qcom,msm-uart";

		reg = <0x19c40000 0x1000>,

		      <0x19c00000 0x1000>;

		interrupts = <195>;

		interrupts = <0 195 0x0>;

	};

};

arch/arm/configs/mini2440_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y 
# CONFIG_BLK_DEV_BSG is not set

CONFIG_BLK_DEV_INTEGRITY=y

CONFIG_ARCH_S3C24XX=y

# CONFIG_CPU_S3C2410 is not set

CONFIG_CPU_S3C2440=y

CONFIG_S3C_ADC=y

CONFIG_S3C24XX_PWM=y

CONFIG_MACH_MINI2440=y

arch/arm/mach-exynos/clock-exynos4.c

+12 −12
Original line number Diff line number Diff line
@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = { 
		.ctrlbit	= (1 << 3),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.0",

		.devname	= "exynos4-sdhci.0",

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 5),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.1",

		.devname	= "exynos4-sdhci.1",

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 6),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.2",

		.devname	= "exynos4-sdhci.2",

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 7),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.3",

		.devname	= "exynos4-sdhci.3",

		.parent		= &exynos4_clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 8),
@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = { 
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.0",

		.devname	= "exynos4-sdhci.0",

		.parent		= &exynos4_clk_dout_mmc0.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 0),
@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = { 
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.1",

		.devname	= "exynos4-sdhci.1",

		.parent		= &exynos4_clk_dout_mmc1.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 4),
@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = { 
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.2",

		.devname	= "exynos4-sdhci.2",

		.parent		= &exynos4_clk_dout_mmc2.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 8),
@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = { 
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.3",

		.devname	= "exynos4-sdhci.3",

		.parent		= &exynos4_clk_dout_mmc3.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 12),
@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { 
	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),

	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),

	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),

	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),

	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),

	CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),

	CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),

	CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),

	CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),

	CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),

	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),

	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),

arch/arm/mach-exynos/clock-exynos5.c

+12 −12
Original line number Diff line number Diff line
@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = { 
		.ctrlbit	= (1 << 20),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.0",

		.devname	= "exynos4-sdhci.0",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 12),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.1",

		.devname	= "exynos4-sdhci.1",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 13),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.2",

		.devname	= "exynos4-sdhci.2",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 14),

	}, {

		.name		= "hsmmc",

		.devname	= "s3c-sdhci.3",

		.devname	= "exynos4-sdhci.3",

		.parent		= &exynos5_clk_aclk_200.clk,

		.enable		= exynos5_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 15),
@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { 
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.0",

		.devname	= "exynos4-sdhci.0",

		.parent		= &exynos5_clk_dout_mmc0.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 0),
@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { 
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.1",

		.devname	= "exynos4-sdhci.1",

		.parent		= &exynos5_clk_dout_mmc1.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 4),
@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { 
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.2",

		.devname	= "exynos4-sdhci.2",

		.parent		= &exynos5_clk_dout_mmc2.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 8),
@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { 
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {

	.clk	= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.3",

		.devname	= "exynos4-sdhci.3",

		.parent		= &exynos5_clk_dout_mmc3.clk,

		.enable		= exynos5_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 12),
@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = { 
	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),

	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),

	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),

	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),

	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),

	CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),

	CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),

	CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),

	CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),

	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),

	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),

	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),

arch/arm/mach-exynos/common.c

+13 −1
Original line number Diff line number Diff line
@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void) 
	s3c_fimc_setname(2, "exynos4-fimc");

	s3c_fimc_setname(3, "exynos4-fimc");



	s3c_sdhci_setname(0, "exynos4-sdhci");

	s3c_sdhci_setname(1, "exynos4-sdhci");

	s3c_sdhci_setname(2, "exynos4-sdhci");

	s3c_sdhci_setname(3, "exynos4-sdhci");



	/* The I2C bus controllers are directly compatible with s3c2440 */

	s3c_i2c0_setname("s3c2440-i2c");

	s3c_i2c1_setname("s3c2440-i2c");
@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void) 
	s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;

	s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;



	s3c_sdhci_setname(0, "exynos4-sdhci");

	s3c_sdhci_setname(1, "exynos4-sdhci");

	s3c_sdhci_setname(2, "exynos4-sdhci");

	s3c_sdhci_setname(3, "exynos4-sdhci");



	/* The I2C bus controllers are directly compatible with s3c2440 */

	s3c_i2c0_setname("s3c2440-i2c");

	s3c_i2c1_setname("s3c2440-i2c");
@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void) 
{

	int irq;



	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);

#ifdef CONFIG_OF

	of_irq_init(exynos4_dt_irq_match);

#endif



	for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {

		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),