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Commit a8f5b6e5 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-fixes-a2-for-3.4rc' of... 

Merge tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes

From Paul Walmsley:

OMAP clock, powerdomain, clockdomain, and hwmod fixes intended for the
early v3.4-rc series.  Also contains an HSMMC integration refinement
of an earlier hardware bug workaround.

* tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending:
  ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions
  ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status
  ARM: OMAP2+: hwmod: Restore sysc after a reset
  ARM: OMAP2+: omap_hwmod: Allow io_ring wakeup configuration for all modules
  ARM: OMAP3: clock data: fill in some missing clockdomains
  ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock
  ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL
  ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch()
  ARM: OMAP AM3517/3505: clock data: change EMAC clocks aliases
  ARM: OMAP: clock: fix race in disable all clocks
  ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocks
  ARM: OMAP3xxx: clock data: fix DPLL4 CLKSEL masks
  ARM: OMAP3xxx: HSMMC: avoid erratum workaround when transceiver is attached
  ARM: OMAP44xx: clockdomain data: correct the emu_sys_clkdm CLKTRCTRL data
parents 1ac02d79 a9dd31b7

arch/arm/mach-omap2/clock3xxx_data.c

+12 −6
Original line number Diff line number Diff line
@@ -747,7 +747,7 @@ static struct clk dpll4_m3_ck = { 
	.parent		= &dpll4_ck,

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),

	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,

	.clksel_mask	= OMAP3630_CLKSEL_TV_MASK,

	.clksel		= dpll4_clksel,

	.clkdm_name	= "dpll4_clkdm",

	.recalc		= &omap2_clksel_recalc,
@@ -832,7 +832,7 @@ static struct clk dpll4_m4_ck = { 
	.parent		= &dpll4_ck,

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),

	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,

	.clksel_mask	= OMAP3630_CLKSEL_DSS1_MASK,

	.clksel		= dpll4_clksel,

	.clkdm_name	= "dpll4_clkdm",

	.recalc		= &omap2_clksel_recalc,
@@ -859,7 +859,7 @@ static struct clk dpll4_m5_ck = { 
	.parent		= &dpll4_ck,

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),

	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,

	.clksel_mask	= OMAP3630_CLKSEL_CAM_MASK,

	.clksel		= dpll4_clksel,

	.clkdm_name	= "dpll4_clkdm",

	.set_rate	= &omap2_clksel_set_rate,
@@ -886,7 +886,7 @@ static struct clk dpll4_m6_ck = { 
	.parent		= &dpll4_ck,

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),

	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,

	.clksel_mask	= OMAP3630_DIV_DPLL4_MASK,

	.clksel		= dpll4_clksel,

	.clkdm_name	= "dpll4_clkdm",

	.recalc		= &omap2_clksel_recalc,
@@ -1394,6 +1394,7 @@ static struct clk cpefuse_fck = { 
	.name		= "cpefuse_fck",

	.ops		= &clkops_omap2_dflt,

	.parent		= &sys_ck,

	.clkdm_name	= "core_l4_clkdm",

	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),

	.enable_bit	= OMAP3430ES2_EN_CPEFUSE_SHIFT,

	.recalc		= &followparent_recalc,
@@ -1403,6 +1404,7 @@ static struct clk ts_fck = { 
	.name		= "ts_fck",

	.ops		= &clkops_omap2_dflt,

	.parent		= &omap_32k_fck,

	.clkdm_name	= "core_l4_clkdm",

	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),

	.enable_bit	= OMAP3430ES2_EN_TS_SHIFT,

	.recalc		= &followparent_recalc,
@@ -1412,6 +1414,7 @@ static struct clk usbtll_fck = { 
	.name		= "usbtll_fck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll5_m2_ck,

	.clkdm_name	= "core_l4_clkdm",

	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),

	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,

	.recalc		= &followparent_recalc,
@@ -1617,6 +1620,7 @@ static struct clk fshostusb_fck = { 
	.name		= "fshostusb_fck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &core_48m_fck,

	.clkdm_name	= "core_l4_clkdm",

	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),

	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,

	.recalc		= &followparent_recalc,
@@ -2043,6 +2047,7 @@ static struct clk omapctrl_ick = { 
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

	.enable_bit	= OMAP3430_EN_OMAPCTRL_SHIFT,

	.flags		= ENABLE_ON_INIT,

	.clkdm_name	= "core_l4_clkdm",

	.recalc		= &followparent_recalc,

};
@@ -2094,6 +2099,7 @@ static struct clk usb_l4_ick = { 
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),

	.clksel_mask	= OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,

	.clksel		= usb_l4_clksel,

	.clkdm_name	= "core_l4_clkdm",

	.recalc		= &omap2_clksel_recalc,

};
@@ -3467,8 +3473,8 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK(NULL,	"ipss_ick",	&ipss_ick,	CK_AM35XX),

	CLK(NULL,	"rmii_ck",	&rmii_ck,	CK_AM35XX),

	CLK(NULL,	"pclk_ck",	&pclk_ck,	CK_AM35XX),

	CLK("davinci_emac",	"emac_clk",	&emac_ick,	CK_AM35XX),

	CLK("davinci_emac",	"phy_clk",	&emac_fck,	CK_AM35XX),

	CLK("davinci_emac",	NULL,	&emac_ick,	CK_AM35XX),

	CLK("davinci_mdio.0",	NULL,	&emac_fck,	CK_AM35XX),

	CLK("vpfe-capture",	"master",	&vpfe_ick,	CK_AM35XX),

	CLK("vpfe-capture",	"slave",	&vpfe_fck,	CK_AM35XX),

	CLK("musb-am35x",	"ick",		&hsotgusb_ick_am35xx,	CK_AM35XX),

arch/arm/mach-omap2/clock44xx_data.c

+3 −2
Original line number Diff line number Diff line
@@ -957,8 +957,8 @@ static struct dpll_data dpll_usb_dd = { 
	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),

	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_USB,

	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_USB,

	.mult_mask	= OMAP4430_DPLL_MULT_MASK,

	.div1_mask	= OMAP4430_DPLL_DIV_MASK,

	.mult_mask	= OMAP4430_DPLL_MULT_USB_MASK,

	.div1_mask	= OMAP4430_DPLL_DIV_0_7_MASK,

	.enable_mask	= OMAP4430_DPLL_EN_MASK,

	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,

	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
@@ -978,6 +978,7 @@ static struct clk dpll_usb_ck = { 
	.recalc		= &omap3_dpll_recalc,

	.round_rate	= &omap2_dpll_round_rate,

	.set_rate	= &omap3_noncore_dpll_set_rate,

	.clkdm_name	= "l3_init_clkdm",

};



static struct clk dpll_usb_clkdcoldo_ck = {

arch/arm/mach-omap2/clockdomains44xx_data.c

+1 −1
Original line number Diff line number Diff line
@@ -390,7 +390,7 @@ static struct clockdomain emu_sys_44xx_clkdm = { 
	.prcm_partition	  = OMAP4430_PRM_PARTITION,

	.cm_inst	  = OMAP4430_PRM_EMU_CM_INST,

	.clkdm_offs	  = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,

	.flags		  = CLKDM_CAN_HWSUP,

	.flags		  = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,

};



static struct clockdomain l3_dma_44xx_clkdm = {

arch/arm/mach-omap2/hsmmc.c

+7 −0
Original line number Diff line number Diff line
@@ -506,6 +506,13 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo, 
	if (oh->dev_attr != NULL) {

		mmc_dev_attr = oh->dev_attr;

		mmc_data->controller_flags = mmc_dev_attr->flags;

		/*

		 * erratum 2.1.1.128 doesn't apply if board has

		 * a transceiver is attached

		 */

		if (hsmmcinfo->transceiver)

			mmc_data->controller_flags &=

				~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;

	}



	pdev = platform_device_alloc(name, ctrl_nr - 1);

arch/arm/mach-omap2/omap_hwmod.c

+38 −50
Original line number Diff line number Diff line
@@ -1479,6 +1479,11 @@ static int _reset(struct omap_hwmod *oh) 


	ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);



	if (oh->class->sysc) {

		_update_sysc_cache(oh);

		_enable_sysc(oh);

	}



	return ret;

}
@@ -1788,20 +1793,9 @@ static int _setup(struct omap_hwmod *oh, void *data) 
		return 0;

	}



	if (!(oh->flags & HWMOD_INIT_NO_RESET)) {

	if (!(oh->flags & HWMOD_INIT_NO_RESET))

		_reset(oh);



		/*

		 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.

		 * The _enable() function should be split to

		 * avoid the rewrite of the OCP_SYSCONFIG register.

		 */

		if (oh->class->sysc) {

			_update_sysc_cache(oh);

			_enable_sysc(oh);

		}

	}



	postsetup_state = oh->_postsetup_state;

	if (postsetup_state == _HWMOD_STATE_UNKNOWN)

		postsetup_state = _HWMOD_STATE_ENABLED;
@@ -1909,20 +1903,10 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) 
 */

int omap_hwmod_softreset(struct omap_hwmod *oh)

{

	u32 v;

	int ret;



	if (!oh || !(oh->_sysc_cache))

	if (!oh)

		return -EINVAL;



	v = oh->_sysc_cache;

	ret = _set_softreset(oh, &v);

	if (ret)

		goto error;

	_write_sysconfig(v, oh);



error:

	return ret;

	return _ocp_softreset(oh);

}



/**
@@ -2465,26 +2449,28 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, 
 * @oh: struct omap_hwmod *

 *

 * Sets the module OCP socket ENAWAKEUP bit to allow the module to

 * send wakeups to the PRCM.  Eventually this should sets PRCM wakeup

 * registers to cause the PRCM to receive wakeup events from the

 * module.  Does not set any wakeup routing registers beyond this

 * point - if the module is to wake up any other module or subsystem,

 * that must be set separately.  Called by omap_device code.  Returns

 * -EINVAL on error or 0 upon success.

 * send wakeups to the PRCM, and enable I/O ring wakeup events for

 * this IP block if it has dynamic mux entries.  Eventually this

 * should set PRCM wakeup registers to cause the PRCM to receive

 * wakeup events from the module.  Does not set any wakeup routing

 * registers beyond this point - if the module is to wake up any other

 * module or subsystem, that must be set separately.  Called by

 * omap_device code.  Returns -EINVAL on error or 0 upon success.

 */

int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)

{

	unsigned long flags;

	u32 v;



	if (!oh->class->sysc ||

	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))

		return -EINVAL;



	spin_lock_irqsave(&oh->_lock, flags);



	if (oh->class->sysc &&

	    (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {

		v = oh->_sysc_cache;

		_enable_wakeup(oh, &v);

		_write_sysconfig(v, oh);

	}



	_set_idle_ioring_wakeup(oh, true);

	spin_unlock_irqrestore(&oh->_lock, flags);
@@ -2496,26 +2482,28 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) 
 * @oh: struct omap_hwmod *

 *

 * Clears the module OCP socket ENAWAKEUP bit to prevent the module

 * from sending wakeups to the PRCM.  Eventually this should clear

 * PRCM wakeup registers to cause the PRCM to ignore wakeup events

 * from the module.  Does not set any wakeup routing registers beyond

 * this point - if the module is to wake up any other module or

 * subsystem, that must be set separately.  Called by omap_device

 * code.  Returns -EINVAL on error or 0 upon success.

 * from sending wakeups to the PRCM, and disable I/O ring wakeup

 * events for this IP block if it has dynamic mux entries.  Eventually

 * this should clear PRCM wakeup registers to cause the PRCM to ignore

 * wakeup events from the module.  Does not set any wakeup routing

 * registers beyond this point - if the module is to wake up any other

 * module or subsystem, that must be set separately.  Called by

 * omap_device code.  Returns -EINVAL on error or 0 upon success.

 */

int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)

{

	unsigned long flags;

	u32 v;



	if (!oh->class->sysc ||

	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))

		return -EINVAL;



	spin_lock_irqsave(&oh->_lock, flags);



	if (oh->class->sysc &&

	    (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {

		v = oh->_sysc_cache;

		_disable_wakeup(oh, &v);

		_write_sysconfig(v, oh);

	}



	_set_idle_ioring_wakeup(oh, false);

	spin_unlock_irqrestore(&oh->_lock, flags);