drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too



Copy&pasted from the vlv setup code. According to docs, we need that
on ivb, too.

v2: Use new masked bit handling macros.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 6b26c86d

drivers/gpu/drm/i915/intel_pm.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -2776,6 +2776,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
		}

		gen7_setup_fixed_func_scheduler(dev_priv);

		/* WaDisable4x2SubspanOptimization */
		I915_WRITE(CACHE_MODE_1,
		_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
		}

		static void valleyview_init_clock_gating(struct drm_device *dev)