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Commit 6b26c86d authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: create macros to handle masked bits 



... and put them to so good use.

Note that there's functional change in vlv clock gating code, we now
no longer spuriously read back the current value of the bit. According
to Bspec the high bits should always read zero, so ORing this in
should have no effect.

Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ee7b9f93

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -438,7 +438,7 @@ void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 
	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))

		udelay(10);



	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);

	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));

	POSTING_READ(FORCEWAKE_MT);



	count = 0;
@@ -480,7 +480,7 @@ void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 


void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);

	I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));

	/* The below doubles as a POSTING_READ */

	gen6_gt_check_fifodbg(dev_priv);

}

drivers/gpu/drm/i915/i915_gem.c

+4 −4
Original line number Diff line number Diff line
@@ -3494,9 +3494,9 @@ void i915_gem_init_swizzling(struct drm_device *dev) 


	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);

	if (IS_GEN6(dev))

		I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));

		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));

	else

		I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));

		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));

}



void i915_gem_init_ppgtt(struct drm_device *dev)
@@ -3545,7 +3545,7 @@ void i915_gem_init_ppgtt(struct drm_device *dev) 
		ecochk = I915_READ(GAM_ECOCHK);

		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |

				       ECOCHK_PPGTT_CACHE64B);

		I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));

		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

	} else if (INTEL_INFO(dev)->gen >= 7) {

		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);

		/* GFX_MODE is per-ring on gen7+ */
@@ -3556,7 +3556,7 @@ void i915_gem_init_ppgtt(struct drm_device *dev) 


		if (INTEL_INFO(dev)->gen >= 7)

			I915_WRITE(RING_MODE_GEN7(ring),

				   GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));

				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));



		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);

		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);

drivers/gpu/drm/i915/i915_irq.c

+2 −3
Original line number Diff line number Diff line
@@ -1648,7 +1648,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe) 


	/* maintain vblank delivery even in deep C-states */

	if (dev_priv->info->gen == 3)

		I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);

		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);



	return 0;
@@ -1722,8 +1722,7 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe) 


	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	if (dev_priv->info->gen == 3)

		I915_WRITE(INSTPM,

			   INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);

		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));



	i915_disable_pipestat(dev_priv, pipe,

			      PIPE_VBLANK_INTERRUPT_ENABLE |

drivers/gpu/drm/i915/i915_reg.h

+3 −5
Original line number Diff line number Diff line
@@ -29,6 +29,9 @@ 


#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))



#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))

#define _MASKED_BIT_DISABLE(a) ((a) << 16)



/*

 * The Bridge device's PCI config space has information about the

 * fb aperture size and the amount of pre-reserved memory.
@@ -425,8 +428,6 @@ 
#define ARB_MODE		0x04030

#define   ARB_MODE_SWIZZLE_SNB	(1<<4)

#define   ARB_MODE_SWIZZLE_IVB	(1<<5)

#define   ARB_MODE_ENABLE(x)	GFX_MODE_ENABLE(x)

#define   ARB_MODE_DISABLE(x)	GFX_MODE_DISABLE(x)

#define RENDER_HWS_PGA_GEN7	(0x04080)

#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)

#define DONE_REG		0x40b0
@@ -514,9 +515,6 @@ 
#define   GFX_PSMI_GRANULARITY		(1<<10)

#define   GFX_PPGTT_ENABLE		(1<<9)



#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))

#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))



#define SCPD0		0x0209c /* 915+ only */

#define IER		0x020a0

#define IIR		0x020a4

drivers/gpu/drm/i915/intel_pm.c

+2 −3
Original line number Diff line number Diff line
@@ -2821,9 +2821,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
		intel_flush_display_plane(dev_priv, pipe);

	}



	I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) |

		   (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) |

		   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);

	I915_WRITE(CACHE_MODE_1,

		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

}



static void g4x_init_clock_gating(struct drm_device *dev)