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Commit fe3e7ab1 authored by Ghanim Fodi's avatar Ghanim Fodi
Browse files

msm: gsi: update IRAM size to 32KB for GSI 2.5 



Update the GSI driver code to return the IRAM
size and offset of new GSI version 2.5.

CRs-Fixed: 2258048
Change-Id: Iac52cfa89199040d7b9254d9e73361badd13db71
Signed-off-by: default avatarGhanim Fodi <gfodi@codeaurora.org>
parent 34ba1341

drivers/platform/msm/gsi/gsi.c

+38 −5
Original line number Diff line number Diff line
@@ -2997,13 +2997,46 @@ int gsi_enable_fw(phys_addr_t gsi_base_addr, u32 gsi_size, enum gsi_ver ver) 
EXPORT_SYMBOL(gsi_enable_fw);



void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset,

		unsigned long *size)

		unsigned long *size, enum gsi_ver ver)

{

	if (base_offset)

		*base_offset = GSI_GSI_INST_RAM_n_OFFS(0);

	unsigned long maxn;



	if (!gsi_ctx) {

		pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__);

		return;

	}



	switch (ver) {

	case GSI_VER_1_0:

	case GSI_VER_1_2:

	case GSI_VER_1_3:

		maxn = GSI_GSI_INST_RAM_n_MAXn;

		break;

	case GSI_VER_2_0:

		maxn = GSI_V2_0_GSI_INST_RAM_n_MAXn;

		break;

	case GSI_VER_2_2:

		maxn = GSI_V2_2_GSI_INST_RAM_n_MAXn;

		break;

	case GSI_VER_2_5:

		maxn = GSI_V2_5_GSI_INST_RAM_n_MAXn;

		break;

	case GSI_VER_ERR:

	case GSI_VER_MAX:

	default:

		GSIERR("GSI version is not supported %d\n", ver);

		WARN_ON(1);

		return;

	}

	if (size)

		*size = GSI_GSI_INST_RAM_n_WORD_SZ *

			(GSI_GSI_INST_RAM_n_MAXn + 1);

		*size = GSI_GSI_INST_RAM_n_WORD_SZ * (maxn + 1);



	if (base_offset) {

		if (ver < GSI_VER_2_5)

			*base_offset = GSI_GSI_INST_RAM_n_OFFS(0);

		else

			*base_offset = GSI_V2_5_GSI_INST_RAM_n_OFFS(0);

	}

}

EXPORT_SYMBOL(gsi_get_inst_ram_offset_and_size);

drivers/platform/msm/gsi/gsi_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -697,8 +697,13 @@ 
#define GSI_GSI_INST_RAM_n_WORD_SZ 0x4

#define GSI_GSI_INST_RAM_n_OFFS(n) \

	(GSI_GSI_REG_BASE_OFFS + 0x00004000 + GSI_GSI_INST_RAM_n_WORD_SZ * (n))

#define GSI_V2_5_GSI_INST_RAM_n_OFFS(n) \

	(GSI_GSI_REG_BASE_OFFS + 0x0001b000 + GSI_GSI_INST_RAM_n_WORD_SZ * (n))

#define GSI_GSI_INST_RAM_n_RMSK 0xffffffff

#define GSI_GSI_INST_RAM_n_MAXn 4095

#define GSI_V2_0_GSI_INST_RAM_n_MAXn 6143

#define GSI_V2_2_GSI_INST_RAM_n_MAXn 4095

#define GSI_V2_5_GSI_INST_RAM_n_MAXn 8191

#define GSI_GSI_INST_RAM_n_INST_BYTE_3_BMSK 0xff000000

#define GSI_GSI_INST_RAM_n_INST_BYTE_3_SHFT 0x18

#define GSI_GSI_INST_RAM_n_INST_BYTE_2_BMSK 0xff0000

drivers/platform/msm/ipa/ipa_v3/ipa.c

+2 −1
Original line number Diff line number Diff line
@@ -4783,7 +4783,8 @@ static int ipa3_manual_load_ipa_fws(void) 


	IPADBG("FWs are available for loading\n");



	result = ipa3_load_fws(fw, ipa3_res.transport_mem_base);

	result = ipa3_load_fws(fw, ipa3_res.transport_mem_base,

		ipa3_get_gsi_ver(ipa3_res.ipa_hw_type));

	if (result) {

		IPAERR("Manual IPA FWs loading has failed\n");

		release_firmware(fw);

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+2 −1
Original line number Diff line number Diff line
@@ -2364,7 +2364,8 @@ int ipa3_uc_panic_notifier(struct notifier_block *this, 
	unsigned long event, void *ptr);

void ipa3_inc_acquire_wakelock(void);

void ipa3_dec_release_wakelock(void);

int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base);

int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base,

	enum gsi_ver);

int ipa3_register_ipa_ready_cb(void (*ipa_ready_cb)(void *), void *user_data);

const char *ipa_hw_error_str(enum ipa3_hw_errors err_type);

int ipa_gsi_ch20_wa(void);

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+10 −2
Original line number Diff line number Diff line
@@ -5933,11 +5933,13 @@ static int ipa3_load_single_fw(const struct firmware *firmware, 
 *

 * @firmware: Structure which contains the FW data from the user space.

 * @gsi_mem_base: GSI base address

 * @gsi_ver: GSI Version

 *

 * Return value: 0 on success, negative otherwise

 *

 */

int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base)

int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base,

	enum gsi_ver gsi_ver)

{

	const struct elf32_hdr *ehdr;

	const struct elf32_phdr *phdr;
@@ -5947,6 +5949,11 @@ int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base) 
	u32 ipa_reg_ofst;

	int rc;



	if (gsi_ver == GSI_VER_ERR) {

		IPAERR("Invalid GSI Version\n");

		return -EINVAL;

	}



	if (!gsi_mem_base) {

		IPAERR("Invalid GSI base address\n");

		return -EINVAL;
@@ -5977,7 +5984,8 @@ int ipa3_load_fws(const struct firmware *firmware, phys_addr_t gsi_mem_base) 
	 */



	/* Load GSI FW image */

	gsi_get_inst_ram_offset_and_size(&gsi_iram_ofst, &gsi_iram_size);

	gsi_get_inst_ram_offset_and_size(&gsi_iram_ofst, &gsi_iram_size,

		gsi_ver);

	if (phdr->p_vaddr != (gsi_mem_base + gsi_iram_ofst)) {

		IPAERR(

			"Invalid GSI FW img load addr vaddr=0x%x gsi_mem_base=%pa gsi_iram_ofst=0x%lx\n"