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Commit fd1adef3 authored by Koji Matsuoka's avatar Koji Matsuoka Committed by Laurent Pinchart
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drm: rcar-du: Fix H/V sync signal polarity configuration 



The VSL and HSL bits in the DSMR register set the corresponding
horizontal and vertical sync signal polarity to active high. The code
got it the wrong way around, fix it.

Signed-off-by: default avatarKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
parent 9cdced8a

drivers/gpu/drm/rcar-du/rcar_du_crtc.c

+2 −2
Original line number Diff line number Diff line
@@ -149,8 +149,8 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) 
	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);



	/* Signal polarities */

	value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)

	      | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)

	value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)

	      | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)

	      | DSMR_DIPM_DISP | DSMR_CSPM;

	rcar_du_crtc_write(rcrtc, DSMR, value);