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Commit 9cdced8a authored by Koji Matsuoka's avatar Koji Matsuoka Committed by Laurent Pinchart
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drm: rcar-du: Fix display timing controller parameter 



There is a bug in the setting of the DES (Display Enable Signal)
register. This current setting occurs 1 dot left shift. The DES
register should be set minus one value about the specifying value
with H/W specification. This patch corrects it.

Signed-off-by: default avatarKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
parent a3c477b3

drivers/gpu/drm/rcar-du/rcar_du_crtc.c

+1 −1
Original line number Diff line number Diff line
@@ -172,7 +172,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) 
					mode->crtc_vsync_start - 1);

	rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);



	rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start);

	rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);

	rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);

}