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Commit fc914639 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: enable and disable PIPE_CLK_SEL at the right time 



Previously we were enabling it at mode_set but never disabling. Let's
follow the mode set sequence.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8d9ddbcb

drivers/gpu/drm/i915/intel_ddi.c

+33 −4
Original line number Original line Diff line number Diff line
@@ -58,6 +58,22 @@ static const u32 hsw_ddi_translations_fdi[] = { 
	0x00FFFFFF, 0x00040006		/* HDMI parameters */

	0x00FFFFFF, 0x00040006		/* HDMI parameters */

};

};





static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)

{

	int type = intel_encoder->type;



	if (type == INTEL_OUTPUT_HDMI) {

		struct intel_hdmi *intel_hdmi =

			enc_to_intel_hdmi(&intel_encoder->base);

		return intel_hdmi->ddi_port;

	} else if (type == INTEL_OUTPUT_ANALOG) {

		return PORT_E;

	} else {

		DRM_ERROR("Invalid DDI encoder type %d\n", type);

		BUG();

	}

}



/* On Haswell, DDI port buffers must be programmed with correct values

/* On Haswell, DDI port buffers must be programmed with correct values

 * in advance. The buffer values are different for FDI and DP modes,

 * in advance. The buffer values are different for FDI and DP modes,

 * but the HDMI/DVI fields are shared among those. So we program the DDI

 * but the HDMI/DVI fields are shared among those. So we program the DDI
@@ -145,8 +161,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 
	/* Use SPLL to drive the output when in FDI mode */

	/* Use SPLL to drive the output when in FDI mode */

	I915_WRITE(PORT_CLK_SEL(PORT_E),

	I915_WRITE(PORT_CLK_SEL(PORT_E),

			PORT_CLK_SEL_SPLL);

			PORT_CLK_SEL_SPLL);

	I915_WRITE(PIPE_CLK_SEL(pipe),

			PIPE_CLK_SEL_PORT(PORT_E));





	udelay(20);

	udelay(20);
@@ -689,8 +703,6 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, 
	 */

	 */

	I915_WRITE(PORT_CLK_SEL(port),

	I915_WRITE(PORT_CLK_SEL(port),

			PORT_CLK_SEL_WRPLL1);

			PORT_CLK_SEL_WRPLL1);

	I915_WRITE(PIPE_CLK_SEL(pipe),

			PIPE_CLK_SEL_PORT(port));





	udelay(20);

	udelay(20);
@@ -825,6 +837,23 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 
	return true;

	return true;

}

}





void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)

{

	struct drm_crtc *crtc = &intel_crtc->base;

	struct drm_i915_private *dev_priv = crtc->dev->dev_private;

	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);

	enum port port = intel_ddi_get_encoder_port(intel_encoder);



	I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_PORT(port));

}



void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)

{

	struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;



	I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_DISABLED);

}



void intel_enable_ddi(struct intel_encoder *encoder)

void intel_enable_ddi(struct intel_encoder *encoder)

{

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_device *dev = encoder->base.dev;

drivers/gpu/drm/i915/intel_display.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -3197,6 +3197,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
		if (encoder->pre_enable)

		if (encoder->pre_enable)

			encoder->pre_enable(encoder);

			encoder->pre_enable(encoder);





	if (IS_HASWELL(dev))

		intel_ddi_enable_pipe_clock(intel_crtc);



	/* Enable panel fitting for LVDS */

	/* Enable panel fitting for LVDS */

	if (dev_priv->pch_pf_size &&

	if (dev_priv->pch_pf_size &&

	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {

	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
@@ -3272,6 +3275,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) 
	I915_WRITE(PF_CTL(pipe), 0);

	I915_WRITE(PF_CTL(pipe), 0);

	I915_WRITE(PF_WIN_SZ(pipe), 0);

	I915_WRITE(PF_WIN_SZ(pipe), 0);





	if (IS_HASWELL(dev))

		intel_ddi_disable_pipe_clock(intel_crtc);



	for_each_encoder_on_crtc(dev, crtc, encoder)

	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->post_disable)

		if (encoder->post_disable)

			encoder->post_disable(encoder);

			encoder->post_disable(encoder);

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -584,5 +584,7 @@ extern void intel_ddi_pll_init(struct drm_device *dev); 
extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);

extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);

extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,

extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,

					enum pipe pipe);

					enum pipe pipe);

extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);

extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);





#endif /* __INTEL_DRV_H__ */
 
#endif /* __INTEL_DRV_H__ */