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Commit 8d9ddbcb authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: enable and disable DDI_FUNC_CTL at the right time 



And the right time is exactly after/before changing PIPE_CONF. See the
documentation about the mode set sequence.

This code is not inside any encoder-specific callback because
DDI_FUNC_CTL is part of the pipe, so it is used by all encoders.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 79f689aa

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4394,6 +4394,7 @@ 
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */

#define  PIPE_DDI_PORT_MASK		(7<<28)

#define  PIPE_DDI_SELECT_PORT(x)	((x)<<28)

#define  PIPE_DDI_PORT_NONE		(0<<28)

#define  PIPE_DDI_MODE_SELECT_MASK	(7<<24)

#define  PIPE_DDI_MODE_SELECT_HDMI	(0<<24)

#define  PIPE_DDI_MODE_SELECT_DVI	(1<<24)

drivers/gpu/drm/i915/intel_ddi.c

+64 −19
Original line number Diff line number Diff line
@@ -203,15 +203,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) 
						DP_TP_CTL_ENHANCED_FRAME_ENABLE |

						DP_TP_CTL_ENABLE);



			/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in FDI mode */

			temp = I915_READ(DDI_FUNC_CTL(pipe));

			temp &= ~PIPE_DDI_PORT_MASK;

			temp |= PIPE_DDI_SELECT_PORT(PORT_E) |

					PIPE_DDI_MODE_SELECT_FDI |

					PIPE_DDI_FUNC_ENABLE |

					PIPE_DDI_PORT_WIDTH_X2;

			I915_WRITE(DDI_FUNC_CTL(pipe),

					temp);

			break;

		} else {

			DRM_ERROR("Error training BUF_CTL %d\n", i);
@@ -657,7 +648,7 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, 
	int port = intel_hdmi->ddi_port;

	int pipe = intel_crtc->pipe;

	int p, n2, r2;

	u32 temp, i;

	u32 i;



	/* On Haswell, we need to enable the clocks and prepare DDI function to

	 * work in HDMI mode for this pipe.
@@ -715,8 +706,40 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, 
		intel_write_eld(encoder, adjusted_mode);

	}



	intel_hdmi->set_infoframes(encoder, adjusted_mode);

}



static struct intel_encoder *

intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_encoder *intel_encoder, *ret = NULL;

	int num_encoders = 0;



	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {

		ret = intel_encoder;

		num_encoders++;

	}



	if (num_encoders != 1)

		WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,

		     intel_crtc->pipe);



	BUG_ON(ret == NULL);

	return ret;

}



void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)

{

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);

	struct drm_i915_private *dev_priv = crtc->dev->dev_private;

	enum pipe pipe = intel_crtc->pipe;

	uint32_t temp;



	/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */

	temp = PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port);

	temp = PIPE_DDI_FUNC_ENABLE;



	switch (intel_crtc->bpp) {

	case 18:
@@ -736,19 +759,41 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, 
		     intel_crtc->bpp);

	}



	if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)

		temp |= PIPE_DDI_PVSYNC;

	if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)

		temp |= PIPE_DDI_PHSYNC;



	if (intel_encoder->type == INTEL_OUTPUT_HDMI) {

		struct intel_hdmi *intel_hdmi =

			enc_to_intel_hdmi(&intel_encoder->base);



		if (intel_hdmi->has_hdmi_sink)

			temp |= PIPE_DDI_MODE_SELECT_HDMI;

		else

			temp |= PIPE_DDI_MODE_SELECT_DVI;



	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)

		temp |= PIPE_DDI_PVSYNC;

	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)

		temp |= PIPE_DDI_PHSYNC;

		temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);

	} else if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {

		temp |= PIPE_DDI_MODE_SELECT_FDI;

		temp |= PIPE_DDI_SELECT_PORT(PORT_E);

	} else {

		WARN(1, "Invalid encoder type %d for pipe %d\n",

		     intel_encoder->type, pipe);

	}



	I915_WRITE(DDI_FUNC_CTL(pipe), temp);

}



	intel_hdmi->set_infoframes(encoder, adjusted_mode);

void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,

				 enum pipe pipe)

{

	uint32_t reg = DDI_FUNC_CTL(pipe);

	uint32_t val = I915_READ(reg);



	val &= ~(PIPE_DDI_FUNC_ENABLE | PIPE_DDI_PORT_MASK);

	val |= PIPE_DDI_PORT_NONE;

	I915_WRITE(reg, val);

}



bool intel_ddi_get_hw_state(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_display.c

+6 −0
Original line number Diff line number Diff line
@@ -3215,6 +3215,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
	 */

	intel_crtc_load_lut(crtc);



	if (IS_HASWELL(dev))

		intel_ddi_enable_pipe_func(crtc);



	intel_enable_pipe(dev_priv, pipe, is_pch_port);

	intel_enable_plane(dev_priv, plane, pipe);
@@ -3262,6 +3265,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) 


	intel_disable_pipe(dev_priv, pipe);



	if (IS_HASWELL(dev))

		intel_ddi_disable_pipe_func(dev_priv, pipe);



	/* Disable PF */

	I915_WRITE(PF_CTL(pipe), 0);

	I915_WRITE(PF_WIN_SZ(pipe), 0);

drivers/gpu/drm/i915/intel_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -581,5 +581,8 @@ extern void intel_ddi_mode_set(struct drm_encoder *encoder, 
				struct drm_display_mode *mode,

				struct drm_display_mode *adjusted_mode);

extern void intel_ddi_pll_init(struct drm_device *dev);

extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);

extern void intel_ddi_disable_pipe_func(struct drm_i915_private *dev_priv,

					enum pipe pipe);



#endif /* __INTEL_DRV_H__ */